Abstract: A substrate processing method is provided. The substrate processing method comprises loading a substrate onto a substrate support inside a chamber, forming a plasma inside the chamber, providing a first DC pulse signal to an electromagnet that generates a magnetic field inside the chamber and processing the substrate with the plasma, wherein the first DC pulse signal is repeated at a first period including a first section and a second section subsequent to the first section, the first DC pulse signal has a first level during the first section, and the first DC pulse signal has a second level different from the first level during the second section.

Abstract: A buffer controller includes a pointer generator, a code converter, a synchronizer, a code restorer, and a comparator. The pointer generator operates according to a first clock signal, and generates a first pointer by encoding a first address of a buffer with a first code. The code converter generates a first transmission pointer by converting the first pointer with a second code or a third code according to an amount of data stored in or read from the first address. The synchronizer synchronizes the first transmission pointer with a second clock signal. The code restorer generates a first comparison pointer by restoring the first transmission pointer, synchronized with the second clock signal, with the first code. The comparator compares the first comparison pointer with a second pointer. The second pointer defines a second address of the buffer with the first code.

Abstract: A buffer controller includes a pointer generator, a code converter, a synchronizer, a code restorer, and a comparator. The pointer generator operates according to a first clock signal, and generates a first pointer by encoding a first address of a buffer with a first code. The code converter generates a first transmission pointer by converting the first pointer with a second code or a third code according to an amount of data stored in or read from the first address. The synchronizer synchronizes the first transmission pointer with a second clock signal. The code restorer generates a first comparison pointer by restoring the first transmission pointer, synchronized with the second clock signal, with the first code. The comparator compares the first comparison pointer with a second pointer. The second pointer defines a second address of the buffer with the first code.

Abstract: The present invention relates to a heat dissipation plate for a projection-type integration circuit (IC) package, which is installed to be adhered and fixed to a projection-type IC package in which an integration circuit in a board is formed to project, so as to dissipate heat generated by the integrated circuit, including: a fixed plate adhered and fixed to the projection-type IC package; and heat dissipation fins (cooling fins) formed to be inclined upward from both opposing sides of the fixed plate, wherein an accommodation groove that accommodates the integrated circuit is formed in a rear surface of the fixed plate, and the accommodation groove is formed to have a shape to be joined to the integrated circuit, and the integrated circuit comes into close contact with the accommodation groove.

Abstract: A method for recycling a wafer is provided. The method removes residues remaining on the wafer separated from a semiconductor layer, using HCl and Cl2 gases under high temperature and low pressure conditions. According to the method, damage of a surface of the wafer is minimized. In addition, since reduction in thickness and an outer diameter of the wafer is minimized, a number of attempts at reprocessing the wafer may be increased.

Abstract: A clock and data recovery (CDR) circuit includes a sampler, a CDR loop and a phase interpolator. The sampler samples serial data in response to a recovery clock signal to generate a serial sampling pulse. The CDR loop transforms the serial sampling pulse into parallel data, generates a plurality of phase signals with a first speed based on the parallel data, and generates a phase control signal with a second speed higher than the first speed based on the plurality of phase signals. The phase interpolator generates the recovery clock signal by controlling a phase of a reference clock signal in response to the phase control signal. Therefore, the CDR circuit may recover data and a clock with a relatively high speed.

Abstract: A clock correction circuit includes a delay locked loop (DLL) configured to delay an external clock signal and to generate an internal clock signal, a first duty cycle correction (DCC) unit configured to correct a duty cycle of the external clock signal in response to a first duty cycle code, a second DCC unit configured to correct a duty cycle of the internal clock signal in response to a second duty cycle code, and a duty cycle code generation unit configured to select an output of from outputs of the first and second DCC Units and to generate the first and second duty cycle codes by detecting a duty cycle ratio of the selected output.

Abstract: A deserializer and method for deserializing data are disclosed. The method includes converting data from a serial data domain to a parallel data domain, detecting a comma related to the parallel data while the data is in the serial data domain, wherein conversion of the data from the serial data domain to the parallel data domain is made in relation to detection of the comma.

Abstract: A deserializer and method for deserializing data are disclosed. The method includes converting data from a serial data domain to a parallel data domain, detecting a comma related to the parallel data while the data is in the serial data domain, wherein conversion of the data from the serial data domain to the parallel data domain is made in relation to detection of the comma.

Abstract: Agents for surface treatment which can impart excellent corrosion resistance to zinc or zinc alloy products at low cost. The agents for the surface treatment of zinc or zinc alloy products of this invention include at least one water-soluble compound which contains antimony, bismuth, tellurium or tin. Ideally, a nickel salt and/or a manganese salt is also included, and most desirably tannins and/or thioureas are also included. Ideally, the zinc or zinc alloy products which have been immersed and treated in an aqueous solution which contains these agents for surface treatment are immersed in an aqueous solution which includes a sealing treatment agent selected according to the colour of the zinc or zinc alloy product to seal pinholes.

Abstract: A clock and data recovery (CDR) circuit includes a sampler, a CDR loop and a phase interpolator. The sampler samples serial data in response to a recovery clock signal to generate a serial sampling pulse. The CDR loop transforms the serial sampling pulse into parallel data, generates a plurality of phase signals with a first speed based on the parallel data, and generates a phase control signal with a second speed higher than the first speed based on the plurality of phase signals. The phase interpolator generates the recovery clock signal by controlling a phase of a reference clock signal in response to the phase control signal. Therefore, the CDR circuit may recover data and a clock with a relatively high speed.

Abstract: A timing cover for an engine includes a plurality of dome-shaped embossed portions formed at positions of the timing cover that are most susceptible to vibration, based on an analysis of vibration modes of the timing cover.

Abstract: Disclosed is a device for calibrating termination voltage of an on-die termination. The device for calibrating termination voltage of an on-die termination for a semiconductor memory device having a DLL device, comprises an on-die termination enable signal generating part for outputting an ODT enable signal for driving the on-die termination (ODT) when a signal DLL Reset EMRS is applied, a counter circuit of for outputting a plurality of counter signals, an on-die termination (ODT) including a variable resistor part controlled by the counter signals outputted from the counter circuit and outputting a variable termination voltage according to a resistance value of the variable resistor part, and a first control part for comparing a reference voltage with the termination voltage and outputting a control signal for controlling the counter circuit according to a comparison result.

Abstract: The apparatus for forming a thin film includes a reaction chamber having a top portion, a sidewall portion and a bottom portion; a gas injector penetrating the top portion and letting a source element pass therethrough; a distributor connected to the gas injector, wherein a plurality of injection holes are formed in the distributor and the source element is injected through the plurality of injection holes; and u substrate heating member positioned in a reaction space defined by the top, bottom and sidewall portions of the reaction chamber, and arranged below the distributor.

Abstract: A hemispherical grain (HSG) capacitor having HSGs on at least a part of the surface of capacitor lower electrodes, and a method of forming the same. In the capacitor, lower electrodes are formed of at least two amorphous silicon layers including an amorphous silicon layer doped with a high concentration of impurities and an amorphous silicon layer doped with a low concentration of impurities, and HSGs are formed, wherein the size of the hemispherical grains can be adjusted such that the size of HSGs formed on the inner surface of a U-shaped lower electrode or on the top of a stacked lower electrode is larger than that of HSGs formed on the outer surface of the U-shaped lower electrode or on the sidews of the stacked lower electrode. Thus, bridging between neighboring lower electrodes can be avoided by appropriately adjusting the size of HSGs, resulting in uniform capacitance wafer-to-wafer and within a wafer. The mechanical strength of the U-shaped lower electrode can also be enhanced.

Abstract: Disclosed is a high density plasma processing apparatus having a resonance antenna coil. The apparatus includes a processing chamber providing a hermetically sealed plasma generating space and having a planar surface on a top wall; a plurality of gas pipes that inject process gases into the processing chamber; a plurality of loop-shaped antennas installed on the planar surface and connected in parallel; a resonance antenna coil receiving a high frequency power and including the plurality of loop-shaped antennas and a plurality of variable capacitor that are connected in parallel with the plurality of loop-shaped antennas in order to maintain a resonance state therebetween; a means for heating the resonance antenna coil by way of using a heat exchange medium; and a means for fixing a substrate inside the processing chamber parallel with the planar surface of the top wall of the processing chamber.

Abstract: According to the present invention, a process of the present invention is performed with stagnated process gas in a chamber. The process comprises the steps of supplying process gas into a chamber, blocking process gas entry and exit from the chamber so as to stagnate the supplied gas therein, and performing the process. As a result, a process time can be significantly reduced, thereby maximizing yield and reducing the substantial amount of the process gas.

Abstract: Integrated circuit capacitors include a U-shaped capacitor electrode on a substrate and an HSG silicon layer extending on an inner surface of the U-shaped capacitor electrode. A HSG protection layer comprising silicon nitride is also provided. The HSG protection layer extends on the HSG silicon layer but not on an outer surface of the U-shaped capacitor electrode. A first capacitor dielectric layer comprising silicon nitride extends on the silicon nitride HSG protection layer and on the outer surface of the U-shaped capacitor electrode. A second capacitor dielectric layer comprising an oxide extends on the first capacitor dielectric layer and an upper capacitor electrode extends on the second capacitor dielectric layer.

Abstract: A cup holder device capable of reducing the size of a cup holder body and enabling a tray to be drawn in and out from the body in a narrow space by folding the tray into two parts. The device includes a body having an opening formed on a front portion of the body, an inner tray for being drawn in and out of the body through the opening, an outer tray installed on a front portion of the inner tray so that both the inner tray and the outer tray provide at least one cup seat, and a hinge section for folding the outer tray over the inner tray so that the inner and outer trays in a folded state are received in the body.