Abstract: Integrated circuit capacitors include a U-shaped capacitor electrode on a substrate and an HSG silicon layer extending on an inner surface of the U-shaped capacitor electrode. A HSG protection layer comprising silicon nitride is also provided. The HSG protection layer extends on the HSG silicon layer but not on an outer surface of the U-shaped capacitor electrode. A first capacitor dielectric layer comprising silicon nitride extends on the silicon nitride HSG protection layer and on the outer surface of the U-shaped capacitor electrode. A second capacitor dielectric layer comprising an oxide extends on the first capacitor dielectric layer and an upper capacitor electrode extends on the second capacitor dielectric layer.

Abstract: A cup holder device capable of reducing the size of a cup holder body and enabling a tray to be drawn in and out from the body in a narrow space by folding the tray into two parts. The device includes a body having an opening formed on a front portion of the body, an inner tray for being drawn in and out of the body through the opening, an outer tray installed on a front portion of the inner tray so that both the inner tray and the outer tray provide at least one cup seat, and a hinge section for folding the outer tray over the inner tray so that the inner and outer trays in a folded state are received in the body.

Abstract: A method of forming a hemispherical grained silicon layer includes the step of forming a first amorphous silicon layer on an integrated circuit substrate by exposing the integrated circuit substrate to a first atmosphere including a silicon source gas and an anti-nucleation gas. A hemispherical grained silicon layer is formed on the amorphous silicon layer opposite the substrate. The anti-nucleation gas can be nitrogen oxide or oxygen.

Abstract: A silicon layer is formed on an integrated circuit substrate using silane and disilane thereby increasing a step coverage for the silicon layer, increasing a deposition rate for the silicon layer, reducing variability of the deposition rate, and reducing local crystallization of the silicon layer. More particularly, the step of forming the silicon layer can include forming a first silicon sublayer on the substrate using a first source gas including silane, and forming a second silicon sublayer on the first silicon sublayer using a second source gas different from the first source gas wherein the second source gas includes disilane. Alternately, the step of forming the silicon layer can include forming the silicon layer on the integrated circuit substrate using a source gas including a mixture of silane and disilane.