Patents by Inventor Bo-Shiun Jiang

Bo-Shiun Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE THEREOF
    Publication number: 20130252374
    Abstract: A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-dis
    Type: Application
    Filed: May 14, 2013
    Publication date: September 26, 2013
    Applicant: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Cheng-Hung Shih, Shu-Chen Lin, Cheng-Fan Lin, Yung-Wei Hsieh, Bo-Shiun Jiang
  • SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE THEREOF
    Publication number: 20130214407
    Abstract: A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-dis
    Type: Application
    Filed: February 16, 2012
    Publication date: August 22, 2013
    Applicant: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Cheng-Hung Shih, Shu-Chen Lin, Cheng-Fan Lin, Yung-Wei Hsieh, Bo-Shiun Jiang
  • Semiconductor packaging method and structure thereof
    Patent number: 8497579
    Abstract: A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-dis
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: July 30, 2013
    Assignee: Chipbond Technology Corporation
    Inventors: Cheng-Hung Shih, Shu-Chen Lin, Cheng-Fan Lin, Yung-Wei Hsieh, Bo-Shiun Jiang