Patents by Inventor Bo Shu
Bo Shu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10510767Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.Type: GrantFiled: September 6, 2019Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yun-Chi Wu, Cheng-Bo Shu, Chien Hung Liu
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Patent number: 10504912Abstract: Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.Type: GrantFiled: February 26, 2018Date of Patent: December 10, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Bo Shu, Chung-Jen Huang, Yun-Chi Wu
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Patent number: 10505015Abstract: A memory device includes a semiconductor substrate and a pair of control gate stacks on the cell region. Each of the control gate stacks includes a storage layer and a control gate on the storage layer. The memory device includes at least one high-? metal gate stack disposed on the substrate. The high-? metal gate stack has a metal gate and a top surface of the control gate is lower than a top surface of the metal gate. The storage layer includes two oxide layers and a nitride layer, and the nitride layer is interposed in between the two oxide layers.Type: GrantFiled: November 17, 2016Date of Patent: December 10, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jing-Ru Lin, Cheng-Bo Shu, Tsung-Yu Yang, Chung-Jen Huang
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Patent number: 10329630Abstract: Compositions and methods for detecting presence of an emerging influenza virus in a sample, such as a biological sample obtained from a subject or an environmental sample, are disclosed. In some embodiments, the compositions and methods can be used to quickly identify particular subtypes of influenza virus (such as a pandemic and/or emerging influenza virus subtype). Probes and primers are provided herein that permit the rapid detection and/or discrimination of pandemic influenza virus subtype nucleic acids in a sample. Devices (such as arrays) and kits for detection and/or discrimination of influenza virus subtype nucleic acids are also provided.Type: GrantFiled: December 7, 2017Date of Patent: June 25, 2019Assignee: The United States of America, as represented by the Secretary, Department of Health and Human ServicesInventors: Bo Shu, Stephen Lindstrom
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Publication number: 20190140108Abstract: A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.Type: ApplicationFiled: November 27, 2018Publication date: May 9, 2019Inventors: Cheng-Bo SHU, Yun-Chi WU, Chung-Jen HUANG
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Patent number: 10276728Abstract: A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.Type: GrantFiled: July 7, 2017Date of Patent: April 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Bo Shu, Yun-Chi Wu, Chung-Jen Huang
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Patent number: 10269822Abstract: The present disclosure relates to a method of forming an embedded flash memory cell that provides for improved performance by providing for a tunnel dielectric layer having a relatively uniform thickness, and an associated apparatus. The method is performed by forming a charge trapping dielectric structure over a logic region, a control gate region, and a select gate region within a substrate. A first charge trapping dielectric etching process is performed to form an opening in the charge trapping dielectric structure over the logic region, and a thermal gate dielectric layer is formed within the opening. A second charge trapping dielectric etching process is performed to remove the charge trapping dielectric structure over the select gate region. Gate electrodes are formed over the thermal gate dielectric layer and the charge trapping dielectric structure remaining after the second charge trapping dielectric etching process.Type: GrantFiled: November 30, 2016Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jui-Yu Pan, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu, Yueh-Chieh Chu
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Publication number: 20190067302Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.Type: ApplicationFiled: March 26, 2018Publication date: February 28, 2019Inventors: Yun-Chi Wu, Cheng-Bo Shu, Chien Hung Liu
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Publication number: 20190043878Abstract: The present disclosure relates to a method of forming an embedded flash memory cell that provides for improved performance by providing for a tunnel dielectric layer having a relatively uniform thickness, and an associated apparatus. The method is performed by forming a charge trapping dielectric structure over a logic region, a control gate region, and a select gate region within a substrate. A first charge trapping dielectric etching process is performed to form an opening in the charge trapping dielectric structure over the logic region, and a thermal gate dielectric layer is formed within the opening. A second charge trapping dielectric etching process is performed to remove the charge trapping dielectric structure over the select gate region. Gate electrodes are formed over the thermal gate dielectric layer and the charge trapping dielectric structure remaining after the second charge trapping dielectric etching process.Type: ApplicationFiled: September 27, 2018Publication date: February 7, 2019Inventors: Jui-Yu Pan, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu, Yueh-Chieh Chu
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Publication number: 20190035799Abstract: Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.Type: ApplicationFiled: February 26, 2018Publication date: January 31, 2019Inventors: Cheng-Bo Shu, Chung-Jen Huang, Yun-Chi Wu
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Publication number: 20190013414Abstract: A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.Type: ApplicationFiled: July 7, 2017Publication date: January 10, 2019Inventors: Cheng-Bo SHU, Yun-Chi Wu, Chung-Jen HUANG
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Patent number: 10170488Abstract: A semiconductor device includes a substrate and a floating gate memory cell. The floating gate memory cell includes an erase gate structure disposed on the substrate, a first floating gate structure, a second floating gate structure, a first word line, a common source, a second word line, a first spacer and a second spacer. The first floating gate structure and the second floating gate structure are recessed in the substrate at two opposite sides of the erase gate structure. The first word line and the second word line are respectively adjacent to the first floating gate structure and the second floating gate structure. The common source is disposed in the substrate under the erase gate structure. The first spacer and the second spacer are respectively disposed between the first floating gate structure and the first word line and between the second floating gate structure and the second word line.Type: GrantFiled: January 9, 2018Date of Patent: January 1, 2019Assignee: TAIWAN SEMICONDUCTOR MANFACTURING CO., LTD.Inventors: Cheng-Bo Shu, Tsung-Yu Yang, Chung-Jen Huang
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Publication number: 20180371527Abstract: Primers, probes and kits for detection of live attenuated influenza vaccine (LAIV) virus strains are provided. Also provided are the assays for detecting LAIV.Type: ApplicationFiled: December 13, 2016Publication date: December 27, 2018Applicant: The United States of America as Represented by the Secretary of the Department of Health and Human SInventors: Bo SHU, Stephen LINDSTROM, Kai-Hui WU, LaShondra BERMAN, Christine WARNES
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Publication number: 20180265936Abstract: The present disclosure relates to compositions and methods for detecting presence of an influenza virus in a sample, such as a biological sample obtained from a subject or an environmental sample. In some embodiments, the compositions and methods can be used to quickly identify particular subtypes of influenza virus (such as seasonal or variant influenza subtype H3, influenza subtype H5, Eurasian influenza subtype H7, North American influenza subtype H7, and/or influenza subtype H9) present in a sample. Probes and primers are provided herein that permit the rapid detection and/or discrimination of influenza virus subtype nucleic acids in a sample. Devices (such as arrays) and kits for detection and/or discrimination of influenza virus subtype nucleic acids are also disclosed herein.Type: ApplicationFiled: May 25, 2018Publication date: September 20, 2018Applicant: The United States of America as represented by the Secretary, Dept. of Health and Human ServicesInventors: Bo Shu, Stephen Lindstrom, Kai-Hui Wu, LaShondra Berman, Shannon L. Emery, Christine Warnes, Catharine McCord
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Patent number: 10006097Abstract: Compositions and methods for detecting presence of an influenza virus in a sample, such as a biological sample obtained from a subject or an environmental sample, are provided. In some embodiments, the compositions and methods can be used to quickly identify particular subtypes of influenza virus (such as seasonal or variant influenza subtype H3, influenza subtype H5, Eurasian influenza subtype H7, North American influenza subtype H7, and/or influenza subtype H9) present in a sample. Probes and primers are provided herein that permit the rapid detection and/or discrimination of influenza virus subtype nucleic acids in a sample. Devices (such as arrays) and kits for detection and/or discrimination of influenza virus subtype nucleic acids are also provided.Type: GrantFiled: October 22, 2014Date of Patent: June 26, 2018Assignee: The United States of America, as represented by the Secretry, Department of Health and Human ServicesInventors: Bo Shu, Stephen Lindstrom, Kai-Hui Wu, LaShondra Berman, Shannon L. Emery, Christine Warnes, Catharine McCord
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Publication number: 20180163277Abstract: Compositions and methods for detecting presence of an emerging influenza virus in a sample, such as a biological sample obtained from a subject or an environmental sample, are disclosed. In some embodiments, the compositions and methods can be used to quickly identify particular subtypes of influenza virus (such as a pandemic and/or emerging influenza virus subtype). Probes and primers are provided herein that permit the rapid detection and/or discrimination of pandemic influenza virus subtype nucleic acids in a sample. Devices (such as arrays) and kits for detection and/or discrimination of influenza virus subtype nucleic acids are also provided.Type: ApplicationFiled: December 7, 2017Publication date: June 14, 2018Applicant: The United States of America, as represented by the Secretary, Dept. of Health and Human ServicesInventors: Bo Shu, Stephen Lindstrom
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Patent number: 9997527Abstract: In a method for manufacturing a semiconductor device, a logic well and a high voltage well are respectively formed in second and third regions of a substrate. A first device structure and a second device structure are formed on a first region of the substrate, third and fourth device structures are respectively formed on the logic well and the high voltage well. A first word line Vt, a source side junction, and a second word line Vt are formed adjacent to the first device structure, between the first device structure and the second device structure, and adjacent to the second device structure. The fourth device structure is removed. A source line junction is formed in the source side junction. The third device structure is removed. First word line and second word lines are respectively formed on the first word line Vt and the second word line Vt.Type: GrantFiled: January 3, 2017Date of Patent: June 12, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Bo Shu, Tsung-Yu Yang, Chung-Jen Huang
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Publication number: 20180151585Abstract: In a method for manufacturing a semiconductor device, a logic well and a high voltage well are respectively formed in second and third regions of a substrate. A first device structure and a second device structure are formed on a first region of the substrate, third and fourth device structures are respectively formed on the logic well and the high voltage well. A first word line Vt, a source side junction, and a second word line Vt are formed adjacent to the first device structure, between the first device structure and the second device structure, and adjacent to the second device structure. The fourth device structure is removed. A source line junction is formed in the source side junction. The third device structure is removed. First word line and second word lines are respectively formed on the first word line Vt and the second word line Vt.Type: ApplicationFiled: January 3, 2017Publication date: May 31, 2018Inventors: Cheng-Bo Shu, Tsung-Yu Yang, Chung-Jen Huang
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Publication number: 20180138317Abstract: A memory device includes a semiconductor substrate and a pair of control gate stacks on the cell region. Each of the control gate stacks includes a storage layer and a control gate on the storage layer. The memory device includes at least one high-? metal gate stack disposed on the substrate. The high-? metal gate stack has a metal gate and a top surface of the control gate is lower than a top surface of the metal gate. The storage layer includes two oxide layers and a nitride layer, and the nitride layer is interposed in between the two oxide layers.Type: ApplicationFiled: November 17, 2016Publication date: May 17, 2018Inventors: Jing-Ru Lin, Cheng-Bo Shu, Tsung-Yu Yang, Chung-Jen Huang
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Publication number: 20180080091Abstract: Primers, probes and kits for detection and lineage differentiation of influenza B virus strains are provided. Also provided are the corresponding assays and methods.Type: ApplicationFiled: September 22, 2017Publication date: March 22, 2018Applicant: THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY, DEPARTMENT OF HEALTH AND HUMANInventors: Shannon Lynn Emery, Stephen Lindstrom, Kai-Hui Wu, LaShondra Shealey Berman, Christine Marie Warnes, Bo Shu