METHOD FOR MANUFACTURING EMBEDDED NON-VOLATILE MEMORY
In a method for manufacturing a semiconductor device, a logic well and a high voltage well are respectively formed in second and third regions of a substrate. A first device structure and a second device structure are formed on a first region of the substrate, third and fourth device structures are respectively formed on the logic well and the high voltage well. A first word line Vt, a source side junction, and a second word line Vt are formed adjacent to the first device structure, between the first device structure and the second device structure, and adjacent to the second device structure. The fourth device structure is removed. A source line junction is formed in the source side junction. The third device structure is removed. First word line and second word lines are respectively formed on the first word line Vt and the second word line Vt.
This application claims priority to U.S. Provisional Application Ser. No. 62/426,681, filed Nov. 28, 2016, which is herein incorporated by reference.
BACKGROUNDThe semiconductor integrated circuit (IC) industry has experienced exponential growth over the last few decades. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.
Super-flash technology has enabled designers to create cost effective and high performance programmable SOC (system on chip) solutions through the use of split-gate flash memory cells. The aggressive scaling of the third generation embedded super-flash (ESF3) memory enables designing flash memories with very high memory array density.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.
Terms used herein are only used to describe the specific embodiments, which are not used to limit the claims appended herewith. For example, unless limited otherwise, the term “one” or “the” of the single form may also represent the plural form. The terms such as “first” and “second” are used for describing various devices, areas and layers, etc., though such terms are only used for distinguishing one device, one area or one layer from another device, another area or another layer. Therefore, the first area can also be referred to as the second area without departing from the spirit of the claimed subject matter, and the others are deduced by analogy. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
In a typical process for manufacturing a 1.5 T ESF3 memory, the 1.5 T ESF3 memory is formed with a polysilicon storage by using a logic first process, i.e. a logic well is formed before a non-volatile memory (NVM) process. The logic well is impacted by the subsequent non-volatile memory process, and resulting in a logic device shift. In another process for manufacturing a 1.5 T ESF3 memory, the 1.5 T ESF3 memory is formed by using a logic last process, i.e. a logic well is formed after a non-volatile memory process, such that the shift of the logic device is decreased. However, in the logic last process, an implantation operation of a low voltage well of a low voltage device is performed through a gate oxide layer of a high voltage device, such that an implant profile of the low voltage well is affected, and resulting in the low voltage device shift. Moreover, the applying of the polysilicon storage induces a triple polysilicon process, and thus increasing complex of the process of manufacturing the 1.5 T ESF3 memory.
Embodiments of the present disclosure are directed to providing a method for manufacturing the semiconductor device, in which after a logic well of a logic device and a high voltage well of a high voltage device are formed, dummy structures are formed to cover the logic well and the high voltage well as device structures are formed, such that the logic well and the high voltage well can be prevented by the dummy structures during subsequent high temperature processes, thereby greatly decreasing shift of the logic device and the high voltage device. Furthermore, an oxide/nitride/oxide (ONO) structure is formed as a trap storage structure of each of device structures, the ONO trap storage structure is thinner than a polysilicon floating gate of a conventional memory, and a control gate of the device structure can be directly disposed on the ONO trap storage structure, such that the thickness of the device structure is reduced. In addition, with the ONO trap storage structure, a triple polysilicon process can be omitted. Thus, compared to the device structure of the conventional memory, each of the device structures has a lower structure topology which is close to that of a logic gate, such that the subsequent patterning processes of the semiconductor device are relatively easy, thereby simplifying a process for manufacturing the semiconductor device and integration of the processes of the semiconductor device and other device, and decreasing process time and reducing process cost.
Referring to
After the isolation structures 102a-102d are completed, a pad oxide layer 106 is blanketly formed to cover the substrate 100 by a deposition method or a thermal oxidization method. In some examples, a logic well 108 is formed in the substrate 100 in the second region 104b by performing an implantation process on the second region 104b. Then, a high voltage well 110 is formed in the substrate 100 in the third region 104c by performing an implantation process on the third region 104c. The logic well 108 and the high voltage well 110 are formed using dopants, such as boron and phosphorous. After the logic well 108 and the high voltage well 110 are completed, the portion of the pad oxide layer 106 in the first region 104a is removed by using a photolithography method and an etching method. The remaining portions of the pad oxide layer 106 cover the second region 104b and the third region 104c, as shown in
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In some examples, the device structure 130d and the gap oxide layers 154 are removed, as shown in
In some examples, after the device structure 130d and the gap oxide layers 154 are removed, a first gate oxide layer 156 is formed to cover the substrate 100. The first gate oxide layer 156 may be formed to further cover the device structures 130a-130c. In some exemplary examples, the first gate oxide layer 156 may be formed to include a rapid thermal oxide (RTO) layer and a high temperature oxide layer on the rapid thermal oxide layer.
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In addition, by using the ONO structure as the trap storage structure 138a and 138b, the semiconductor device 184 can be programmed using a source side injection (SSI) programming method, and can be erased using a Fowler-Nordheim (FN) erase method, thereby decreasing power consumption of the semiconductor device 184. Furthermore, because the semiconductor device 184 can be programmed by a SSI programming method, the programming operation of the semiconductor device 184 can be performed by a byte mode.
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A pad oxide layer 106 is blanketly formed to cover the substrate 100 by a deposition method or a thermal oxidization method. At operation 202, referring to
At operation 206, as shown in
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At operation 208, as shown in
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At operation 210, as shown in
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At operation 214, as shown in
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Various lightly doped drains 176a-176g may be optionally formed in the substrate 100 by using an implantation method. The lightly doped drains 176a and 176b are formed in the logic well 108 at opposite sides of the gate 168 and adjacent to the gate 168, the lightly doped drain 176c is formed in the word line Vt 142 adjacent the word line 164, the lightly doped drain 176d is formed in the word line Vt 146 adjacent the word line 166, the lightly doped drains 176e and 176f are formed in the high voltage well 110 at opposite sides of the gate 172 and adjacent to the gate 172, and the lightly doped drain 176g is formed in the source line junction 158.
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In accordance with an embodiment, the present disclosure discloses a method for manufacturing a semiconductor device. In this method, various isolation structures are formed in a substrate to at least define a first region, a second region, and a third region. A logic well and a high voltage well are respectively formed in the second region and the third region. A first device structure and a second device structure are formed on the first region, a third device structure is formed to cover the logic well, and a fourth device structure is formed to cover the high voltage well. A first word line Vt, a source side junction, and a second word line Vt are formed in the first region, in which the first word line Vt and the second word line Vt are respectively adjacent to the first device structure and the second device structure, and the source side junction is located between the first device structure and the second device structure, and is opposite to the first word line Vt and the second word line Vt respectively. The fourth device structure is removed. A source line junction is formed in the source side junction. The third device structure is removed. A first word line and a second word line are respectively formed on the first word line Vt adjacent to the first device structure and the second word line Vt adjacent to the second device structure.
In accordance with another embodiment, the present disclosure discloses a method for manufacturing a semiconductor device. In this method, various isolation structures are formed in a substrate to at least define a first region, a second region, and a third region. A logic well and a high voltage well are respectively formed in the second region and the third region. A first device structure and a second device structure are formed on the first region, a third device structure is formed to cover the logic well, and a fourth device structure is formed to cover the high voltage well. Gap oxide layers are formed on sidewalls of the first device structure, the second device structure, the third device structure, and the fourth device structure. The fourth device structure and the gap oxide layers on the sidewalls of the fourth device structure are removed. A first gate oxide layer is formed to cover the substrate. The gap oxide layers on the sidewall of the first device structure adjacent to the second device structure, the sidewall of the second device structure adjacent to the first device structure, and the sidewalls of the third device structure are removed. A source line junction is formed in the substrate between the first device structure and the second device structure. The third device structure is removed. A second gate oxide layer is formed on the substrate and the first gate oxide layer. Portions of the second gate oxide layer and portions of the first gate oxide layer on the first region and the second region are removed. A third gate oxide layer is formed to cover the first region, the second region, and the third region. A first word line and a second word line are respectively formed on the gap oxide layer on the first device structure and the gap oxide layer on the second device structure.
In accordance with yet another embodiment, the present disclosure discloses a method for manufacturing a semiconductor device. In this method, various isolation structures are formed in a substrate to at least define a first region, a second region, and a third region. A logic well and a high voltage well are respectively formed in the second region and the third region. A first device structure and a second device structure are formed on the first region, a third device structure is formed to cover the logic well, and a fourth device structure is formed to cover the high voltage well. In forming each of the first device structure, the second device structure, the third device structure, and the fourth device structure, a trap storage structure is formed on the substrate, a control gate is directly formed on the trap storage structure, a cap structure is formed on the control gate to form a stacked structure, and various spacers are respectively formed on sidewalls of the stacked structure. A first word line Vt, a source side junction, and a second word line Vt are formed in the first region, in which the first word line Vt and the second word line Vt are respectively adjacent to the first device structure and the second device structure, and the source side junction is located between the first device structure and the second device structure, and is opposite to the first word line Vt and the second word line Vt respectively. Various gap oxide layers are formed on sidewalls of the first device structure, the second device structure, the third device structure, and the fourth device structure. The fourth device structure and the gap oxide layers on the sidewalls of the fourth device structure are removed. A first gate oxide layer is formed to cover the substrate. The gap oxide layers on the sidewall of the first device structure adjacent to the second device structure, the sidewall of the second device structure adjacent to the first device structure, and the sidewalls of the third device structure are removed. A source line junction is formed in the substrate between the first device structure and the second device structure. The third device structure is removed. A second gate oxide layer is formed on the substrate and the first gate oxide layer. Portions of the second gate oxide layer and portions of the first gate oxide layer on the first region and the second region are removed. A third gate oxide layer is formed to cover the first region, the second region, and the third region A first word line is formed on the gap oxide layer on the first device structure, a second word line is formed on the gap oxide layer on the second device structure, a gate of a high voltage device is formed on the high voltage well, and a gate of a logic device is formed on the logic well.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims
1. A method for manufacturing a semiconductor device, the method comprising:
- forming a plurality of isolation structures in a substrate to at least define a first region, a second region, and a third region;
- forming a logic well and a high voltage well respectively in the second region and the third region;
- forming a first device structure and a second device structure on the first region, a third device structure covering the logic well, and a fourth device structure covering the high voltage well;
- forming a first implanted area, a source side junction, and a second implanted area in the first region, wherein the first implanted area and the second implanted area are respectively adjacent to the first device structure and the second device structure, and the source side junction is located between the first device structure and the second device structure, and is opposite to the first implanted area and the second implanted area respectively;
- removing the fourth device structure;
- forming a source line junction in the source side junction;
- removing the third device structure; and
- forming a first word line and a second word line respectively on the first implanted area adjacent to the first device structure and the second implanted area adjacent to the second device structure.
2. The method of claim 1, wherein forming each of the first device structure, the second device structure, the third device structure, and the fourth device structure further comprise:
- forming a trap storage structure on the substrate;
- forming a control gate directly on the trap storage structure; and
- forming a cap structure on the control gate to form a stacked structure.
3. The method of claim 2, wherein forming the trap storage structure further comprises:
- forming a first oxide layer on the substrate;
- forming a nitride layer on the first oxide layer; and
- forming a second oxide layer on the nitride layer.
4. The method of claim 2, wherein forming the cap structure further comprises:
- forming a first nitride layer on the control gate;
- forming an oxide layer on the first nitride layer; and
- forming a second nitride layer on the oxide layer.
5. The method of claim 2, wherein forming each of the first device structure and the second device structure further comprises:
- forming a plurality of spacers respectively on a plurality of sidewalls of the stacked structure.
6. The method of claim 5, wherein forming each of the spacers further comprises:
- forming a first oxide layer;
- forming a nitride layer on the first oxide layer; and
- forming a second oxide layer on the nitride layer.
7. The method of claim 1,
- after forming the first implanted area, the source side junction, and the second implanted area, the method further comprising forming a plurality of gap oxide layers on sidewalls of the first device structure and the second device structure; and
- between removing the fourth device structure and forming the source line, the method further comprising removing the gap oxide layers on the source side junction.
8. The method of claim 1,
- between removing the fourth device structure and forming the source line junction, the method further comprising forming a first gate oxide layer to cover the substrate; and
- between removing the third device structure and forming the first word line and the second word line, the method further comprising:
- forming a second gate oxide layer on the substrate and the first gate oxide layer;
- removing portions of the second gate oxide layer and portions of the first gate oxide layer on the first region and the second region to expose the first implanted area, the second implanted area, the first device structure, the second device structure, the source line junction, and the logic well; and
- forming a third gate oxide layer on the second gate oxide layer, the first implanted area, the second implanted area, the first device structure, the second device structure, the source line junction, and the logic well.
9. The method of claim 1, wherein forming the first word line and the second word line comprises forming a gate of a high voltage device on the third region and a gate of a logic device on the second region.
10. A method for manufacturing a semiconductor device, the method comprising:
- forming a plurality of isolation structures in a substrate to at least define a first region, a second region, and a third region;
- forming a logic well and a high voltage well respectively in the second region and the third region;
- forming a first device structure and a second device structure on the first region, a third device structure covering the logic well, and a fourth device structure covering the high voltage well;
- forming a plurality of gap oxide layers on sidewalls of the first device structure, the second device structure, the third device structure, and the fourth device structure;
- removing the fourth device structure and the gap oxide layers on the sidewalls of the fourth device structure;
- forming a first gate oxide layer to cover the substrate;
- removing the gap oxide layers on the sidewall of the first device structure adjacent to the second device structure, the sidewall of the second device structure adjacent to the first device structure, and the sidewalls of the third device structure;
- forming a source line junction in the substrate between the first device structure and the second device structure;
- removing the third device structure;
- forming a second gate oxide layer on the substrate and the first gate oxide layer;
- removing portions of the second gate oxide layer and portions of the first gate oxide layer on the first region and the second region;
- forming a third gate oxide layer to cover the first region, the second region, and the third region; and
- forming a first word line and a second word line respectively on the gap oxide layer on the first device structure and the gap oxide layer on the second device structure.
11. The method of claim 10, wherein forming each of the first device structure, the second device structure, the third device structure, and the fourth device structure further comprises:
- forming a trap storage structure on the substrate;
- forming a control gate directly on the trap storage structure; and
- forming a cap structure on the control gate to form a stacked structure.
12. The method of claim 11, wherein forming the trap storage structure further comprises:
- forming a first oxide layer on the substrate;
- forming a nitride layer on the first oxide layer; and
- forming a second oxide layer on the nitride layer.
13. The method of claim 11, wherein forming the cap structure further comprises:
- forming a first nitride layer on the control gate;
- forming an oxide layer on the first nitride layer; and
- forming a second nitride layer on the oxide layer.
14. The method of claim 11, wherein forming each of the first device structure and the second device structure further comprises:
- forming a plurality of spacers respectively on a plurality of sidewalls of the stacked structure.
15. The method of claim 14, wherein forming each of the spacers further comprises:
- forming a first oxide layer;
- forming a nitride layer on the first oxide layer; and
- forming a second oxide layer on the nitride layer.
16. The method of claim 11, between forming the first device structure, the second device structure, the third device structure, and the fourth device structure, and forming the gap oxide layers, the method further comprising:
- forming a first implanted area, a source side junction, and a second implanted area in the first region, wherein the first implanted area and the second implanted area are respectively adjacent to the first device structure and the second device structure, and the source side junction is located between the first device structure and the second device structure, and is opposite to the first implanted area and the second implanted area respectively.
17. A method for manufacturing a semiconductor device, the method comprising:
- forming a plurality of isolation structures in a substrate to at least define a first region, a second region, and a third region;
- forming a logic well and a high voltage well respectively in the second region and the third region;
- forming a first device structure and a second device structure on the first region, a third device structure covering the logic well, and a fourth device structure covering the high voltage well, wherein forming each of the first device structure, the second device structure, the third device structure, and the fourth device structure further comprises:
- forming a trap storage structure on the substrate;
- forming a control gate directly on the trap storage structure;
- forming a cap structure on the control gate to form a stacked structure; and
- forming a plurality of spacers respectively on a plurality of sidewalls of the stacked structure;
- forming a first implanted area, a source side junction, and a second implanted area in the first region, wherein the first implanted area and the second implanted area are respectively adjacent to the first device structure and the second device structure, and the source side junction is located between the first device structure and the second device structure, and is opposite to the first implanted area and the second implanted area respectively;
- forming a plurality of gap oxide layers on sidewalls of the first device structure, the second device structure, the third device structure, and the fourth device structure;
- removing the fourth device structure and the gap oxide layers on the sidewalls of the fourth device structure;
- forming a first gate oxide layer to cover the substrate;
- removing the gap oxide layers on the sidewall of the first device structure adjacent to the second device structure, the sidewall of the second device structure adjacent to the first device structure, and the sidewalls of the third device structure;
- forming a source line junction in the substrate between the first device structure and the second device structure;
- removing the third device structure;
- forming a second gate oxide layer on the substrate and the first gate oxide layer;
- removing portions of the second gate oxide layer and portions of the first gate oxide layer on the first region and the second region;
- forming a third gate oxide layer to cover the first region, the second region, and the third region; and
- forming a first word line on the gap oxide layer on the first device structure, a second word line on the gap oxide layer on the second device structure, a gate of a high voltage device on the high voltage well, and a gate of a logic device on the logic well.
18. The method of claim 17, wherein forming the trap storage structure further comprises:
- forming a first oxide layer on the substrate;
- forming a nitride layer on the first oxide layer; and
- forming a second oxide layer on the nitride layer.
19. The method of claim 17, wherein forming the cap structure further comprises:
- forming a first nitride layer on the control gate;
- forming an oxide layer on the first nitride layer; and
- forming a second nitride on the oxide layer.
20. The method of claim 17, wherein forming each of the spacers further comprises:
- forming a first oxide layer;
- forming a nitride layer on the first oxide layer; and
- forming a second oxide layer on the nitride layer.
Type: Application
Filed: Jan 3, 2017
Publication Date: May 31, 2018
Inventors: Cheng-Bo Shu (Tainan City), Tsung-Yu Yang (Tainan City), Chung-Jen Huang (Tainan City)
Application Number: 15/396,886