Abstract: There is provided a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure.

Abstract: There is provided a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure.

Abstract: Disclosed herein is an image classification method and apparatus for a preset tour camera. More particularly, according to the image classification method and apparatus for a preset tour camera, a classification group is generated not to be duplicated by analyzing feature information included in image frames continuously taken by a preset tour camera that has panning, tilting, and zooming functions, and the image frames are classified by the classification group based on the feature information and stored with an index, whereby when an accident occurs and image analysis is required, the image frames are searched for based on the classification group, thus the image analysis may be conveniently and quickly performed.

Abstract: There is provided a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure.

Abstract: There is provided a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure.

Abstract: Methods are provided for manufacturing semiconductor devices include forming a first fin protruding on a substrate and extending in a first direction; forming first and second sacrificial gate insulating layers on the first fin, the first and second sacrificial gate insulating layers intersecting the first fin and being spaced apart from each other; forming first and second sacrificial gate electrodes respectively on the first and second sacrificial gate insulating layers; forming a first insulating layer on the first and second sacrificial gate electrodes; removing a portion of the first insulating layer to expose the second sacrificial gate electrode; removing the exposed second sacrificial gate electrode using a first etching process to expose the second sacrificial gate insulating layer; removing the exposed second sacrificial gate insulating layer using a second etching process different from the first etching process to form a first trench which exposes the first fin; forming a first recess in the expos

Abstract: Disclosed herein is an image classification method and apparatus for a preset tour camera. More particularly, according to the image classification method and apparatus for a preset tour camera, a classification group is generated not to be duplicated by analyzing feature information included in image frames continuously taken by a preset tour camera that has panning, tilting, and zooming functions, and the image frames are classified by the classification group based on the feature information and stored with an index, whereby when an accident occurs and image analysis is required, the image frames are searched for based on the classification group, thus the image analysis may be conveniently and quickly performed.

Abstract: Described is a semiconductor package frame including a material comprising wire openings a die-mounting surface area with a die-mounting surface and identification markings included within the die-mounting surface. The identification markings uniquely identify the semiconductor package frame from among other semiconductor package frames comprising different identification markings.

Abstract: An embodiment of the present invention is directed to a semiconductor packaging frame allowing identification information to be stored in the paddle area of the individual frame. Forming identification information on the paddle allows unique tracking of the semiconductor frame package during and after manufacturing and for tracking down variances, defects, and other problems during the semiconductor packaging process. Further, the shapes formed from the identification information provide increased surface area for bonding of the molding compound and thus strengthen the bond between the die paddle and molding compound thereby improving the strength of the semiconductor package.

Abstract: In one embodiment, an integrated circuit package includes a lead frame with a die paddle and several leads. Portions of the lead frame not having an external electrical connection may be thinned such that they may be encapsulated by an electrically insulating packaging material on the back of the lead frame. Portions of the lead frame having external electrical connections may have a thickness such that they are exposed through the packaging material. The lead frame may be covered by an electrically insulating cover to protect components on the lead frame from erroneous electrical contact or electro-static discharge (ESD) damage.

Abstract: A semiconductor device package, a method of fabricating a semiconductor device package and a method of testing an integrated circuit utilizing a semiconductor device package are disclosed. Embodiments create a flip-flop semiconductor device package by coupling a semiconductor device, with a wire-bonded arrangement of conductive pads, in a face-up orientation beneath etched portions of multiple leadfingers. The flip-flop package offers improved signaling properties, durability, reliability, and package density at reduced cost given that the conductive pads of the device couple directly to the leadfingers, without requiring the manufacture of a new device or the rerouting of signal paths. The height of the package is also reduced by utilizing space beneath the etched portions of the leadfingers that was unused in conventional solutions. Additionally, the flip-flop configuration provides convenient means for exposing surfaces of the device and/or surfaces of the leadfingers.

Abstract: A semiconductor device package, a method of fabricating a semiconductor device package and a method of testing an integrated circuit utilizing a semiconductor device package are disclosed. Embodiments create a flip-flop semiconductor device package by coupling multiple leadfingers to conductive pads of a semiconductor device using an interposer with electrically conductive traces. The semiconductor device may be positioned in a face-up orientation between the leadfingers such that a single surface of the interposer may couple to both the semiconductor device and the leadfingers. The flip-flop package offers improved signaling properties, durability, reliability, and package density at reduced cost given that the interposer is configurable, the traces offer more reliable and durable interconnections, the interposer enables use of a smaller semiconductor device with a higher density conductive pad arrangement to decrease package density, and the interposer is relatively inexpensive.

Abstract: A method and system for controlling the processing of an IC chip assembly line using a central computer system and a common communication protocol. In one embodiment, a manufacturing execution system (MES) is used as the computer system and the communications protocol is the standard semi equipment communications standard/generic equipment model (SECS/GEM). One or more equipment cell controllers (CC) may be used to communicate between the MES a plurality of in-line substations which comprise the assembly line. Automated vision camera systems may also communicate information to the MES via the CCs. In one embodiment, the MES maintains a database in memory comprising processing history of a die-strip and results of automated die-strip examination from the vision camera systems. In one embodiment, the die-strip may be of a ball grid array (BGA) type.

Abstract: An integrated back-end integrated circuit (IC) manufacturing assembly is disclosed. In one embodiment, the present invention has a front-of-line portion comprising a plurality of integrated sub-stations for operating on a first plurality of die-strips on an in-line basis to produce a second plurality of die-strips. The present embodiment further comprises an end-of-line portion coupled to the front-of-line portion and comprising a plurality of integrated sub-stations for operating on the second plurality of die-strips on an in-line basis to produce die-strip components. The present embodiment also comprises an in-line test portion coupled to the end-of-line portion for testing the die-strip components. The present embodiment further comprises a finish portion coupled to the in-line test portion and comprising a plurality of integrated sub-stations operating on tested die-strip components.