Abstract: A micro light-emitting diode package structure is provided. The micro light-emitting diode package structure includes a plurality of micro light-emitting diode chips, a light-transmitting layer, a first insulating layer, a driving element, and a redistribution layer. The micro light-emitting diode chips are disposed side by side, wherein each micro light-emitting diode chip includes an electrode surface and a light-emitting surface opposite to each other. The light-transmitting layer covers the light-emitting surfaces of the micro light-emitting diode chips. The first insulating layer is disposed below the micro light-emitting diode chips. The driving element is disposed in the first insulating layer, wherein the driving element includes a plurality of electrodes, and the electrodes are on the side of the driving element away from the micro light-emitting diode chips.

Abstract: This invention provides a method for detecting object, which comprises receiving an image; and executing a deep neural network architecture for the image to obtain one or more object bounding box, wherein the deep neural network architecture comprises a two-dimensional discrete wavelet transform.

Abstract: A method for object and key-point detection, comprising: receiving an image, executing a deep neural network architecture for the image to obtain one or more object bounding boxes; executing the deep neural network architecture for the one or more object bounding boxes to obtain one or more key-point positions corresponding to the one or more object bounding boxes; and outputting the one or more object bounding boxes and the one or more key-point positions.

Abstract: This disclosure provides a method for determining visual and auditory attentiveness of vehicle driver, which comprises: determining a visual attentiveness of a driver according to an image captured by a camera installed inside the vehicle; determining a recognition attentiveness of the driver according to sounds obtained by a microphone installed inside the vehicle; deciding whether to issue a reminder to the driver based on the visual attentiveness and the recognition attentiveness of the driver; when it is necessary to remind the driver after determining the driver's visual and recognition attentiveness, one or a combination of reminder steps will be executed; the reminder steps comprising: issuing a visual reminder by a display device in the vehicle; and issuing a auditory reminder by a speaker in the vehicle.

Abstract: A wafer with micro integrated circuits includes a transparent substrate and a plurality of micro components. The micro components are each attached to the transparent substrate by a plurality of transparent adhesive layers. Each of the micro components includes a bonding pad in direct contact with the transparent adhesive layer and an etching stop layer located on the side of the micro components opposite from the bonding pad.

Abstract: The present invention provides a driving assistance system and a driving assistance computation method that utilize a deep neural network architecture to achieve object detection and semantic segmentation functionalities in a single inference of the same model.

Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a gate electrode layer on the p-type semiconductor layer, and patterning the gate electrode layer to form a gate electrode. Preferably, the gate electrode includes an inclined sidewall.

Abstract: A method for manufacturing a high electron mobility transistor device includes providing a substrate. A channel material, a barrier material, a polarization adjustment material and a conductive material are formed on the substrate. A hard mask layer is formed on the conductive material. The conductive material is patterned to form a conductive layer by using the hard mask layer as a mask. A plurality of protection layers is formed on sidewalls of the hard mask layer and the conductive layer. The polarization adjustment material is patterned to form a polarization adjustment layer by using the plurality of protection layers and the hard mask as masks. The plurality of protection layers is removed. A portion of the conductive layer is laterally removed to form a first gate conductive layer.

Abstract: A device includes feed-forward clock circuitry to provide a receiver (RX) clock to a sampler circuit that samples a data lane of a set of RX data lanes, the feed-forward clock circuitry having a temperature-induced delay. The device also includes an RX phase-locked loop (PLL) coupled between the feed-forward clock circuitry and the sampler circuit. The RX PLL includes a phase interpolator positioned in a feedback path of the RX PLL. The phase interpolator has a negative delay that matches the temperature-induced delay of the feed-forward clock circuitry to cause the sampler circuit to cancel out the common noise shared between the feed-forward clock circuitry and the data lane.

Abstract: A light-emitting device, including a mount substrate, at least one light emitting element, a first light transparent member, a second light transparent member and a covering member, is disclosed. The at least one light emitting element is disposed on the mount substrate in a flip-chip manner. The first light transparent member is configured to receive the incident light emitting from the light emitting element, wherein the first light transparent member is formed of an inorganic substance and an inorganic phosphor, and includes a top surface and a first side surface contiguous to the top surface. The second light transparent member is disposed on the top surface of the first light transparent member and is formed of the inorganic substance and contains no the inorganic phosphor, and includes an externally exposed light emission surface and a second side surface contiguous to the externally exposed light emission surface.

Abstract: A phase-locked loop (PLL) device includes a first phase detector to receive an in-phase reference clock and an in-phase feedback clock, the first phase detector to output a first phase error; a second phase detector to receive a quadrature reference clock and a quadrature feedback clock, the second phase detector to output a second phase error; a proportional path component to generate first current pulses from the first phase error and second current pulses from the second phase error; an integrator circuit coupled to the proportional path component, the integrator circuit to sum, within a current output signal, the first current pulses and the second current pulses; a ring oscillator to be driven by the current output signal; and a pair of phase interpolators coupled to an output of the ring oscillator, the pair of phase interpolators to respectively generate the in-phase feedback clock and the quadrature feedback clock.

Abstract: A device includes feed-forward clock circuitry to provide a receiver (RX) clock to a sampler circuit that samples a data lane of a set of RX data lanes, the feed-forward clock circuitry having a temperature-induced delay. The device also includes an RX phase-locked loop (PLL) coupled between the feed-forward clock circuitry and the sampler circuit. The RX PLL includes a phase interpolator positioned in a feedback path of the RX PLL. The phase interpolator has a negative delay that matches the temperature-induced delay of the feed-forward clock circuitry to cause the sampler circuit to cancel out the common noise shared between the feed-forward clock circuitry and the data lane.

Abstract: A phase-locked loop (PLL) device includes a first phase detector to receive an in-phase reference clock and an in-phase feedback clock, the first phase detector to output a first phase error; a second phase detector to receive a quadrature reference clock and a quadrature feedback clock, the second phase detector to output a second phase error; a proportional path component to generate first current pulses from the first phase error and second current pulses from the second phase error; an integrator circuit coupled to the proportional path component, the integrator circuit to sum, within a current output signal, the first current pulses and the second current pulses; a ring oscillator to be driven by the current output signal; and a pair of phase interpolators coupled to an output of the ring oscillator, the pair of phase interpolators to respectively generate the in-phase feedback clock and the quadrature feedback clock.

Abstract: Alight-emitting diode includes an epitaxial unit, a first electrode, and a second electrode. One of the first electrode and the second electrode includes a first reflective layer, a wire-bonding electrode layer, a second reflective layer wrapping a portion of the wire-bonding electrode layer, and a stress adjustment layer which wraps around the first reflective layer. The first reflective layer includes platinum, and the second reflective layer includes a material which has a Mohs hardness of not less than 6. The stress adjustment layer has a Mohs hardness of not less than 6, and the stress adjustment layer has a thickness that is 65% to 75% of a thickness of the first reflective layer.

Abstract: A USB switching circuit includes a first multiplexer, a second multiplexer coupled with the first multiplexer through transmission paths, and a voltage regulation circuit coupled with the first and second multiplexers. The first multiplexer distributes first data signals to the transmission paths according to first control signals. The second multiplexer distributes a second data signal to the transmission paths according to second control signals. The voltage regulation circuit sets a maximum voltage and a minimum voltage of the first data signals to corresponding to a common voltage. The maximum voltage of the first data signals is not higher than a maximum voltage of the second control signals, or the minimum voltage of the first data signals is not lower than a minimum voltage of the second control signals. The first data signals and the second data signal are generated according to different communication protocols.

Abstract: The present disclosure provides a clock data recovery apparatus. The clock data recovery apparatus includes a phase detection circuit, a digital filter, a phase-interpolating circuit and an oscillator circuit. The phase detection circuit receives and samples a data signal according to multiple reference clock signals having different phases, to generate a phase detection result. The digital filter performs accumulation on the phase detection result, to generate a phase-adjusting signal. The phase interpolator circuit performs phase adjustment on a source clock signal according to the phase-adjusting signal, in order to generate an injection clock signal. The oscillator circuit generates the reference clock signals according to the injection clock signal, in which the phases of the reference clock signals follow the phase of the injection clock signal.

Abstract: A light-emitting device, including a mount substrate, at least one light emitting element, a first light transparent member, a second light transparent member and a covering member, is disclosed. The at least one light emitting element is disposed on the mount substrate in a flip-chip manner. The first light transparent member is configured to receive the incident light emitting from the light emitting element, wherein the first light transparent member is formed of an inorganic substance and an inorganic phosphor, and includes a top surface and a first side surface contiguous to the top surface. The second light transparent member is disposed on the top surface of the first light transparent member and is formed of the inorganic substance and contains no the inorganic phosphor, and includes an externally exposed light emission surface and a second side surface contiguous to the externally exposed light emission surface.

Abstract: A USB switching circuit includes a first multiplexer, a second multiplexer coupled with the first multiplexer through transmission paths, and a voltage regulation circuit coupled with the first and second multiplexers. The first multiplexer distributes first data signals to the transmission paths according to first control signals. The second multiplexer distributes a second data signal to the transmission paths according to second control signals. The voltage regulation circuit sets a maximum voltage and a minimum voltage of the first data signals to corresponding to a common voltage. The maximum voltage of the first data signals is not higher than a maximum voltage of the second control signals, or the minimum voltage of the first data signals is not lower than a minimum voltage of the second control signals. The first data signals and the second data signal are generated according to different communication protocols.

Abstract: The present disclosure provides a clock data recovery apparatus. The clock data recovery apparatus includes a phase detection circuit, a digital filter, a phase-interpolating circuit and an oscillator circuit. The phase detection circuit receives and samples a data signal according to multiple reference clock signals having different phases, to generate a phase detection result. The digital filter performs accumulation on the phase detection result, to generate a phase-adjusting signal. The phase interpolator circuit performs phase adjustment on a source clock signal according to the phase-adjusting signal, in order to generate an injection clock signal. The oscillator circuit generates the reference clock signals according to the injection clock signal, in which the phases of the reference clock signals follow the phase of the injection clock signal.

Abstract: An equalizer circuit includes a first arithmetic circuit, a second arithmetic circuit, a data sampling circuit, and an edge sampling circuit. The first arithmetic circuit is configured to compensate an equalization sequence by secondary feedback sequences to output a first added sequence. The second arithmetic circuit is configured to compensate the first added sequence by a primary feedback sequence to output a second added sequence. The data sampling circuit samples, according to data clock, the second added sequence to output a primary sequence, and gains the primary sequence to output the primary feedback sequence. The data sampling circuit sequentially samples, according to the data clock, the primary sequence to output secondary sequences. The data sampling circuit gains the corresponding secondary sequences to output the secondary feedback sequences. The edge sampling circuit is configured to sequentially sample, according to an edge clock, the first added sequence to output an edge sequence.