Patents by Inventor Bo-Yu Lai

Bo-Yu Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210166564
    Abstract: System, methods, and other embodiments described herein relate to providing a warning from a subject vehicle to surrounding objects about a collision hazard. In one embodiment, a method includes identifying the surrounding objects of a subject vehicle according to sensor data about a surrounding environment of the subject vehicle. The method includes determining a collision probability indicating a likelihood of collision between a first object and a second object of the surrounding objects. The method includes, in response to the collision probability satisfying a collision threshold, communicating, by the subject vehicle, an alert to at least one of the surrounding objects about the collision hazard associated with the surrounding objects colliding.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 3, 2021
    Inventors: Ryo Takaki, Ting-Yu Lai, Bo Sun
  • Publication number: 20210134985
    Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.
    Type: Application
    Filed: December 14, 2020
    Publication date: May 6, 2021
    Inventors: Sai-Hooi Yeong, Sheng-Chen Wang, Bo-Yu Lai, Ziwei Fang, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20210118749
    Abstract: A semiconductor device includes a gate stack, an epitaxy structure, a first spacer, a second spacer, and a dielectric residue. The gate stack is over a substrate. The epitaxy structure is formed raised above the substrate. The first spacer is on a sidewall of the gate stack. The first spacer and the epitaxy structure define an air gap therebetween. The second spacer seals the air gap between the first spacer and the epitaxy structure. The dielectric residue is in the air gap and has an upper portion and a lower portion under the upper portion. The upper portion of the dielectric residue has higher etch resistance to phosphoric acid than that of the lower portion of the dielectric residue.
    Type: Application
    Filed: December 7, 2020
    Publication date: April 22, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bo-Yu LAI, Kai-Hsuan LEE, Wei-Yang LEE, Feng-Cheng YANG, Yen-Ming CHEN
  • Publication number: 20210057546
    Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.
    Type: Application
    Filed: November 5, 2020
    Publication date: February 25, 2021
    Inventors: Wen-Kai Lin, Bo-Yu Lai, Li Chun Te, Kai-Hsuan Lee, Sai-Hooi Yeong, Tien-I Bao, Wei-Ken Lin
  • Patent number: 10923565
    Abstract: In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: February 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Hsuan Lee, Bo-Yu Lai, Sai-Hooi Yeong, Feng-Cheng Yang, Yih-Ann Lin, Yen-Ming Chen
  • Publication number: 20210043751
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The FinFET device structure also includes an epitaxial source/drain (S/D) structure formed over the fin structure. A top surface and a sidewall of the fin structure are surrounded by the epitaxial S/D structure. A first distance between an outer surface of the epitaxial S/D structure and the sidewall of the fin structure is no less than a second distance between the outer surface of the epitaxial S/D structure and the top surface of the fin structure.
    Type: Application
    Filed: October 29, 2020
    Publication date: February 11, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sai-Hooi YEONG, Chi-On CHUI, Bo-Feng YOUNG, Bo-Yu LAI, Kuan-Lun CHENG, Chih-Hao WANG
  • Patent number: 10868151
    Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sai-Hooi Yeong, Sheng-Chen Wang, Bo-Yu Lai, Ziwei Fang, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 10861753
    Abstract: A method includes forming a gate stack over a semiconductor substrate, forming a first spacer layer on a sidewall of the gate stack, forming a sacrificial spacer film over the first spacer layer, forming an epitaxy structure on the semiconductor substrate, and performing an etching process on the sacrificial spacer film to form a gap between the first spacer layer and the epitaxy structure. An outer portion of the sacrificial spacer film has a topmost end higher than that of an inner portion of the sacrificial spacer film after performing the etching process. The method further includes forming a second spacer layer to seal the gap between the epitaxy structure and the first spacer layer.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bo-Yu Lai, Kai-Hsuan Lee, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 10833167
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The FinFET device structure also includes an epitaxial source/drain (S/D) structure formed over the fin structure. A top surface and a sidewall of the fin structure are surrounded by the epitaxial S/D structure. A first distance between an outer surface of the epitaxial S/D structure and the sidewall of the fin structure is no less than a second distance between the outer surface of the epitaxial S/D structure and the top surface of the fin structure.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: November 10, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sai-Hooi Yeong, Chi-On Chui, Bo-Feng Young, Bo-Yu Lai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10833170
    Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Kai Lin, Bo-Yu Lai, Li Chun Te, Kai-Hsuan Lee, Sai-Hooi Yeong, Tien-I Bao, Wei-Ken Lin
  • Publication number: 20200287042
    Abstract: A method includes forming a metal gate in a first inter-layer dielectric, performing a treatment on the metal gate and the first inter-layer dielectric, selectively growing a hard mask on the metal gate without growing the hard mask from the first inter-layer dielectric, depositing a second inter-layer dielectric over the hard mask and the first inter-layer dielectric, planarizing the second inter-layer dielectric and the hard mask, and forming a gate contact plug penetrating through the hard mask to electrically couple to the metal gate.
    Type: Application
    Filed: May 27, 2020
    Publication date: September 10, 2020
    Inventors: Kai-Hsuan Lee, Bo-Yu Lai, Sheng-Chen Wang, Sai-Hooi Yeong, Yen-Ming Chen, Chi On Chui
  • Patent number: 10686075
    Abstract: A method includes forming a metal gate in a first inter-layer dielectric, performing a treatment on the metal gate and the first inter-layer dielectric, selectively growing a hard mask on the metal gate without growing the hard mask from the first inter-layer dielectric, depositing a second inter-layer dielectric over the hard mask and the first inter-layer dielectric, planarizing the second inter-layer dielectric and the hard mask, and forming a gate contact plug penetrating through the hard mask to electrically couple to the metal gate.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Hsuan Lee, Bo-Yu Lai, Sheng-Chen Wang, Sai-Hooi Yeong, Yen-Ming Chen, Chi On Chui
  • Publication number: 20200161297
    Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. A top portion of the semiconductor fin is formed of a first semiconductor material. A semiconductor cap layer is formed on a top surface and sidewalls of the semiconductor fin. The semiconductor cap layer is formed of a second semiconductor material different from the first semiconductor material. The method further includes forming a gate stack on the semiconductor cap layer, forming a gate spacer on a sidewall of the gate stack, etching a portion of the semiconductor fin on a side of the gate stack to form a first recess extending into the semiconductor fin, recessing the semiconductor cap layer to form a second recess directly underlying a portion of the gate spacer, and performing an epitaxy to grow an epitaxy region extending into both the first recess and the second recess.
    Type: Application
    Filed: June 3, 2019
    Publication date: May 21, 2020
    Inventors: Yen-Ting Chen, Bo-Yu Lai, Chien-Wei Lee, Hsueh-Chang Sung, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20200152522
    Abstract: A method includes forming a gate dielectric layer on a semiconductor fin, and forming a gate electrode over the gate dielectric layer. The gate electrode extends on sidewalls and a top surface of the semiconductor fin. A gate spacer is selectively deposited on a sidewall of the gate electrode. An exposed portion of the gate dielectric layer is free from a same material for forming the gate spacer deposited thereon. The method further includes etching the gate dielectric layer using the gate spacer as an etching mask to expose a portion of the semiconductor fin, and forming an epitaxy semiconductor region based on the semiconductor fin.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Inventors: Kai-Hsuan Lee, Chia-Ta Yu, Cheng-Yu Yang, Sheng-Chen Wang, Bo-Yu Lai, Bo-Cyuan Lu, Chi On Chui, Sai-Hooi Yeong, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20200135590
    Abstract: A method includes forming a gate stack over a semiconductor substrate, forming a first spacer layer on a sidewall of the gate stack, forming a sacrificial spacer film over the first spacer layer, forming an epitaxy structure on the semiconductor substrate, and performing an etching process on the sacrificial spacer film to form a gap between the first spacer layer and the epitaxy structure. An outer portion of the sacrificial spacer film has a topmost end higher than that of an inner portion of the sacrificial spacer film after performing the etching process. The method further includes forming a second spacer layer to seal the gap between the epitaxy structure and the first spacer layer.
    Type: Application
    Filed: May 14, 2019
    Publication date: April 30, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bo-Yu LAI, Kai-Hsuan LEE, Wei-Yang LEE, Feng-Cheng YANG, Yen-Ming CHEN
  • Publication number: 20200135883
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The FinFET device structure also includes an epitaxial source/drain (S/D) structure formed over the fin structure. A top surface and a sidewall of the fin structure are surrounded by the epitaxial S/D structure. A first distance between an outer surface of the epitaxial S/D structure and the sidewall of the fin structure is no less than a second distance between the outer surface of the epitaxial S/D structure and the top surface of the fin structure.
    Type: Application
    Filed: January 25, 2019
    Publication date: April 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sai-Hooi YEONG, Chi-On CHUI, Bo-Feng YOUNG, Bo-Yu LAI, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20200105867
    Abstract: In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 2, 2020
    Inventors: Kai-Hsuan Lee, Bo-Yu Lai, Sai-Hooi Yeong, Feng-Cheng Yang, Yih-Ann Lin, Yen-Ming Chen
  • Publication number: 20200035809
    Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.
    Type: Application
    Filed: October 4, 2019
    Publication date: January 30, 2020
    Inventors: Wen-Kai Lin, Bo-Yu Lai, Li Chun Te, Kai-Hsuan Lee, Sai-Hooi Yeong, Tien-I Bao, Wei-Ken Lin
  • Patent number: 10535569
    Abstract: A method includes forming a gate dielectric layer on a semiconductor fin, and forming a gate electrode over the gate dielectric layer. The gate electrode extends on sidewalls and a top surface of the semiconductor fin. A gate spacer is selectively deposited on a sidewall of the gate electrode. An exposed portion of the gate dielectric layer is free from a same material for forming the gate spacer deposited thereon. The method further includes etching the gate dielectric layer using the gate spacer as an etching mask to expose a portion of the semiconductor fin, and forming an epitaxy semiconductor region based on the semiconductor fin.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Hsuan Lee, Chia-Ta Yu, Cheng-Yu Yang, Sheng-Chen Wang, Bo-Yu Lai, Bo-Cyuan Lu, Chi On Chui, Sai-Hooi Yeong, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 10490650
    Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: November 26, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Kai Lin, Bo-Yu Lai, Li Chun Te, Kai-Hsuan Lee, Sai-Hooi Yeong, Tien-I Bao, Wei-Ken Lin