Abstract: A computer-implemented method for instrumentation-assisted debugging is provided. The computer-implemented method includes compiling a hardware design to generate a compiled design, generating, from the compiled design, code for the hardware design and debug assist elements, feeding the code into a vendor emulation flow that outputs a vendor waveform and transforming the vendor waveform into a logic simulation waveform that is compatible with a hardware design language (HDL) using the debug assist elements for hardware logic debugging.

Abstract: Error protection analysis of an integrated circuit includes receiving a design model for the integrated circuit, and a list of error checkers associated with the design model. The design model is traversed from each of the error checkers to group storage cells of the design model into checking groups. The design model is updated to include, for each checking group, a unique group identifier associated with each of the storage cells in the checking group.

Abstract: Error protection analysis of an integrated circuit includes receiving a design model for the integrated circuit, and a list of error checkers associated with the design model. The design model is traversed from each of the error checkers to group storage cells of the design model into checking groups. The design model is updated to include, for each checking group, a unique group identifier associated with each of the storage cells in the checking group.

Abstract: Aspects of the invention include systems and methods for to detecting security vulnerabilities using modeled attribute propagation. A non-limited example of a computer-implemented method includes generating a model of a device under test, the model comprising a data path similar to the device under test and an attribute network. The method further includes detecting protected data that is introduced into the model and marking the protected data with an attribute. An end point of the marked protected data is detected along the data path. In response to the end point being indicative of a vulnerability, an alert is issued.

Abstract: A non-limiting example of a computer-implemented method for error injection includes executing a pre-silicon operation on a simulated chip verifying that a plurality of latches from a timing simulation set error checkers when run against a manufacturing test suite in order to generate a cross-reference file containing latch entries in a table. It executes a first post-silicon operation on a hardware chip based on the simulated chip to determine empirically that timing latches from logic built-in self tests (“LBIST”) trigger the same error checkers set by the plurality of latches verified in the simulated chip. The method updates the cross-reference file based on the results of the determination. The method executes a second post-silicon operation on the hardware chip to improve chip frequency by working around functional checkers using the cross-reference file and updating the cross-reference file based on the results of the improving.

Abstract: Aspects of the invention include systems and methods for to detecting security vulnerabilities using modeled attribute propagation. A non-limited example of a computer-implemented method includes generating a model of a device under test, the model comprising a data path similar to the device under test and an attribute network. The method further includes detecting protected data that is introduced into the model and marking the protected data with an attribute. An end point of the marked protected data is detected along the data path. In response to the end point being indicative of a vulnerability, an alert is issued.

Abstract: A non-limiting example of a computer-implemented method for error injection includes executing a pre-silicon operation on a simulated chip verifying that a plurality of latches from a timing simulation set error checkers when run against a manufacturing test suite in order to generate a cross-reference file containing latch entries in a table. It executes a first post-silicon operation on a hardware chip based on the simulated chip to determine empirically that timing latches from logic built-in self tests (“LBIST”) trigger the same error checkers set by the plurality of latches verified in the simulated chip. The method updates the cross-reference file based on the results of the determination. The method executes a second post-silicon operation on the hardware chip to improve chip frequency by working around functional checkers using the cross-reference file and updating the cross-reference file based on the results of the improving.

Abstract: Verifying architectural compliance of a processor core using processor-sparing functions. A simulation of a model for a register-transfer level design of the processor core is performed. A first state of the model is dumped, when no error exists. An error is injected in the model. A second state of the model is dumped, after the injected error is detected in the simulation. Upon dumping the second state, the model is reset and initialized with the first state. State information of the second state is loaded in the reset and initialized model.

Abstract: A method and apparatus for ranking combinations of mutants, test cases and random seeds in mutation testing, comprising obtaining, based on a signal of a test case target, logic gates related to the signal of the test case target and mutants on the related logic gates, for a compiled integrated circuit under test; calculating distances between the mutants and the signal of the test case target; performing a circuit simulation on the compiled integrated circuit under test to obtain activation cycle numbers corresponding to combinations of the mutants, test cases and random seeds; obtaining activation cycle number variances corresponding to combinations of the mutants and the test cases; and ranking the combinations of the mutants, the test cases and the random seeds based on the distances, the activation cycle numbers and the activation cycle number variances. The invention can reduce the probability that the mutation simulation selects equivalent mutants.

Abstract: A simulation environment benchmarks processors to determine processor performance. A benchmark program is instrumented with a microarchitecture instruction. A first clock cycle indicative of a processor before executing the benchmark program is captured. The benchmark program is executed and a processor return related to the microarchitecture instruction is intercepted. In response to the processor return, a second clock cycle indicative of the processor after executing the benchmark program is captured. The simulation environment determines the performance of the processor from the first clock cycle and the second clock cycle.

Abstract: A simulation environment benchmarks processors to determine processor performance. A benchmark program is instrumented with a microarchitecture instruction. A first clock cycle indicative of a processor before executing the benchmark program is captured. The benchmark program is executed and a processor return related to the microarchitecture instruction is intercepted. In response to the processor return, a second clock cycle indicative of the processor after executing the benchmark program is captured. The simulation environment determines the performance of the processor from the first clock cycle and the second clock cycle.

Abstract: Verifying architectural compliance of a processor core using processor-sparing functions. A simulation of a model for a register-transfer level design of the processor core is performed. A first state of the model is dumped, when no error exists. An error is injected in the model. A second state of the model is dumped, after the injected error is detected in the simulation. Upon dumping the second state, the model is reset and initialized with the first state. State information of the second state is loaded in the reset and initialized model.

Abstract: Verifying architectural compliance of a processor core using processor-sparing functions. A simulation of a model for a register-transfer level design of the processor core is performed. A first state of the model is dumped, when no error exists. An error is injected in the model. A second state of the model is dumped, after the injected error is detected in the simulation. Upon dumping the second state, the model is reset and initialized with the first state. State information of the second state is loaded in the reset and initialized model.

Abstract: Verifying architectural compliance of a processor core using processor-sparing functions. A simulation of a model for a register-transfer level design of the processor core is performed. A first state of the model is dumped, when no error exists. An error is injected in the model. A second state of the model is dumped, after the injected error is detected in the simulation. Upon dumping the second state, the model is reset and initialized with the first state. State information of the second state is loaded in the reset and initialized model.

Abstract: A method and apparatus for ranking combinations of mutants, test cases and random seeds in mutation testing, comprising obtaining, based on a signal of a test case target, logic gates related to the signal of the test case target and mutants on the related logic gates, for a compiled integrated circuit under test; calculating distances between the mutants and the signal of the test case target; performing a circuit simulation on the compiled integrated circuit under test to obtain activation cycle numbers corresponding to combinations of the mutants, test cases and random seeds; obtaining activation cycle number variances corresponding to combinations of the mutants and the test cases; and ranking the combinations of the mutants, the test cases and the random seeds based on the distances, the activation cycle numbers and the activation cycle number variances. The invention can reduce the probability that the mutation simulation selects equivalent mutants.

Abstract: A method and apparatus for ranking combinations of mutants, test cases and random seeds in mutation testing, comprising obtaining, based on a signal of a test case target, logic gates related to the signal of the test case target and mutants on the related logic gates, for a compiled integrated circuit under test; calculating distances between the mutants and the signal of the test case target; performing a circuit simulation on the compiled integrated circuit under test to obtain activation cycle numbers corresponding to combinations of the mutants, test cases and random seeds; obtaining activation cycle number variances corresponding to combinations of the mutants and the test cases; and ranking the combinations of the mutants, the test cases and the random seeds based on the distances, the activation cycle numbers and the activation cycle number variances. The invention can reduce the probability that the mutation simulation selects equivalent mutants.

Abstract: Some embodiments include a method for processing a scan chain in an integrated circuit, the method comprising receiving, in the integrated circuit, the scan chain, wherein the scan chain includes a secret key pattern; separating the secret key pattern from the scan chain; storing the scan chain in a first plurality of latches; storing the secret key pattern in a second plurality of latches; comparing the secret key pattern to a reference key pattern, the reference key pattern stored in a third plurality of latches; determining, based on the comparing the secret key pattern to the reference key pattern, that the secret key pattern does not match the reference key pattern; and generating a signal indicating that the secret key pattern does not match the reference key pattern.

Abstract: A computer-implemented method may include retrieving a design netlist with a processor, identifying, via the processor, a logic structure in the design netlist, generating, via the processor, a driver based on the logic structure, applying, via the processor, a simulation and a formal model based on the driver, and testing, via the processor, an output of the simulation and the formal model.

Abstract: A computer-implemented method may include retrieving a design netlist with a processor, identifying, via the processor, a logic structure in the design netlist, generating, via the processor, a driver based on the logic structure, applying, via the processor, a simulation and a formal model based on the driver, and testing, via the processor, an output of the simulation and the formal model.

Abstract: Determining a quality parameter for a verification environment for a register-transfer level hardware design language description of a hardware design. A netlist is generated from the hardware design language description. A list of hardware design outputs is generated, and logical paths in the netlist are generated based on the list of hardware design outputs. Furthermore, a modified netlist involving logical paths is generated by determining whether a gate is selected as an insertion point, and selecting a fault type, which is part of the efficiency vector for the selected gate in the netlist and inserting a mutant. Additionally, a fault simulation is performed and the quality parameter for the verification environment is determined from the fault simulation and the simulation result data.