Abstract: A method and apparatus for ranking combinations of mutants, test cases and random seeds in mutation testing, comprising obtaining, based on a signal of a test case target, logic gates related to the signal of the test case target and mutants on the related logic gates, for a compiled integrated circuit under test; calculating distances between the mutants and the signal of the test case target; performing a circuit simulation on the compiled integrated circuit under test to obtain activation cycle numbers corresponding to combinations of the mutants, test cases and random seeds; obtaining activation cycle number variances corresponding to combinations of the mutants and the test cases; and ranking the combinations of the mutants, the test cases and the random seeds based on the distances, the activation cycle numbers and the activation cycle number variances. The invention can reduce the probability that the mutation simulation selects equivalent mutants.

Abstract: Some embodiments include a method for processing a scan chain in an integrated circuit. The method can include: receiving, in the integrated circuit, the scan chain, wherein the scan chain includes a secret key pattern; separating the secret key pattern from the scan chain; comparing the secret key pattern to a reference key pattern; determining, based on the comparing the secret key pattern to the reference key pattern, that the secret key pattern does not match the reference key pattern; and generating a signal indicating that the secret key pattern does not match the reference key pattern.

Abstract: A simulation environment verifies processor-sparing functions in a simulated processor core. The simulation environment executes a first simulation for a simulated processor core. During the simulation, the simulation environment creates a simulation model dump file. At a later point in time, the simulation environment executes a second simulation for the simulated processor core. The simulation environment saves the state of the simulated processor core. The simulation environment then replaces the state of the simulated processor core by loading the previously created simulation model dump file. The simulation environment then sets the state of the simulated processor core to execute processor-sparing code and resumes the second simulation.

Abstract: Determining a quality parameter for a verification environment for a register-transfer level hardware design language description of a hardware design. A netlist is generated from the hardware design language description. A list of hardware design outputs is generated, and logical paths in the netlist are generated based on the list of hardware design outputs. Furthermore, a modified netlist involving logical paths is generated by determining whether a gate is selected as an insertion point, and selecting a fault type, which is part of the efficiency vector for the selected gate in the netlist and inserting a mutant. Additionally, a fault simulation is performed and the quality parameter for the verification environment is determined from the fault simulation and the simulation result data.

Abstract: A simulation environment verifies processor-sparing functions in a simulated processor core. The simulation environment executes a first simulation for a simulated processor core. During the simulation, the simulation environment creates a simulation model dump file. At a later point in time, the simulation environment executes a second simulation for the simulated processor core. The simulation environment saves the state of the simulated processor core. The simulation environment then replaces the state of the simulated processor core by loading the previously created simulation model dump file. The simulation environment then sets the state of the simulated processor core to execute processor-sparing code and resumes the second simulation.

Abstract: A simulation environment verifies processor-sparing functions in a simulated processor core. The simulation environment executes a first simulation for a simulated processor core. During the simulation, the simulation environment creates a simulation model dump file. At a later point in time, the simulation environment executes a second simulation for the simulated processor core. The simulation environment saves the state of the simulated processor core. The simulation environment then replaces the state of the simulated processor core by loading the previously created simulation model dump file. The simulation environment then sets the state of the simulated processor core to execute processor-sparing code and resumes the second simulation.

Abstract: A simulation environment verifies processor-sparing functions in a simulated processor core. The simulation environment executes a first simulation for a simulated processor core. During the simulation, the simulation environment creates a simulation model dump file. At a later point in time, the simulation environment executes a second simulation for the simulated processor core. The simulation environment saves the state of the simulated processor core. The simulation environment then replaces the state of the simulated processor core by loading the previously created simulation model dump file. The simulation environment then sets the state of the simulated processor core to execute processor-sparing code and resumes the second simulation.

Abstract: Some embodiments include a method for processing a scan chain in an integrated circuit. The method can include: receiving, in the integrated circuit, the scan chain, wherein the scan chain includes a secret key pattern; separating the secret key pattern from the scan chain; comparing the secret key pattern to a reference key pattern; determining, based on the comparing the secret key pattern to the reference key pattern, that the secret key pattern does not match the reference key pattern; and generating a signal indicating that the secret key pattern does not match the reference key pattern.

Abstract: The present invention relates to a system for verifying the proper operation of a digital logic circuit and program product therefore. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of: a) marking a net with an additional property other than a bit value, wherein both said bit value and said additional property are valid at said net at a given time; b) propagating the marking of the net according to a set of predetermined semantic rules, wherein the set of predetermined semantic rules are defined according to a predetermined simulation; and c) generating an output at a predetermined downstream location of the digital logic circuit, said output providing an information, if or if not said property has propagated through the circuit to said predetermined downstream location or not.

Abstract: The present invention relates to a system for verifying the proper operation of a digital logic circuit and program product therefor. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of: a) marking a net with an additional property other than a bit value, wherein both said bit value and said additional property are valid at said net at a given time; b) propagating the marking of the net according to a set of predetermined semantic rules, wherein the set of predetermined semantic rules are defined according to a predetermined simulation; and c) generating an output at a predetermined downstream location of the digital logic circuit, said output providing an information, if or if not said property has propagated through the circuit to said predetermined downstream location or not.

Abstract: The present invention relates to a method for verifying the proper operation of a digital logic circuit. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of: a) marking a net with an additional property other than a bit value, wherein both said bit value and said additional property are valid at said net at a given time; b) propagating the marking of the net according to a set of predetermined semantic rules, wherein the set of predetermined semantic rules are defined according to a predetermined simulation aim; and c) generating an output at a predetermined downstream location of the digital logic circuit, said output providing an information, if or if not said property has propagated through the circuit to said predetermined downstream location or not.

Abstract: The present invention relates to the field of computer hardware locic circuits, and in particular to a method for verifying the proper operation of a digital logic circuit, and in particular to symbolic simulation of a gate-level netlist corresponding to said hardware logic circuit. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of: a) analyzing symbolic expressions visible at predetermined locations within said logic; b) determining, which nets in the netlist carry complex symbolic expressions, which comprise more than one symbol; c) replacing said complex expressions with a “crunshed color”, for cutting off said complex symbolic expression from further propagation through the netlist; d) continuing said symbolic simulation including said crunched color information on predetermined nets.

Abstract: The present invention relates to a method for verifying the proper operation of a digital logic circuit. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of: a) marking a net with an additional property other than the bit value, both, bit value and additional property being valid at said net at a given time, b) propagating the marking of the net according to a set of predetermined semantic rules, wherein the rules are defined according to a predetermined simulation aim, c) generating an output at a predetermined downstream location of the circuit, said output providing an information, if or if not said property has propagated through the circuit to said predetermined circuit location.

Abstract: The present invention relates to the field of computer hardware locic circuits, and in particular to a method for verifying the proper operation of a digital logic circuit, and in particular to symbolic simulation of a gate-level netlist corresponding to said hardware logic circuit. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of: a) analyzing symbolic expressions visible at predetermined locations within said logic, b) determining, which nets in the netlist carry complex symbolic expressions, which comprise more than one symbol, c) replacing said complex expressions with a “crunshed color”, for cutting off said complex symbolic expression from further propagation through the netlist, d) continuing said symbolic simulation including said crunched color information on predetermined nets.