Abstract: A row decoder includes first and second main wordline driving circuits, which are configured to generate respective first and second driving signals onto corresponding first and second main wordlines extending adjacent to each other. In addition, a first transistor within the first main wordline driving circuit and a second transistor within the second main wordline driving circuit have the same function, but extend in different rows when viewed in a direction perpendicular to a substrate on which the first and second main wordlines are formed.

Abstract: A bit line sense amplifier of a semiconductor memory device includes: sense amplifier blocks including a PMOS driver or an NMOS driver that detects and amplifies a signal difference between a bit line and a complimentary bit line, and sequentially arranged in a bit line extending direction; column selection units that connect the bit line and a local input/output line according to a first column selection signal; complimentary column selection units that connect the complimentary bit line and a complimentary local input/output line according to a second column selection signal; column selection lines that transmit the first column selection signal to each of the column selection units; and complimentary column selection lines that transmit the second column selection signal to each of the complimentary column selection units. The column selection units and the complimentary column selection units may be disposed to be distributed between the sense amplifier blocks.

Abstract: A bitline sense amplifier including: an amplifier which is connected between a first sensing bitline and a second sensing bitline, and detects and amplifies a voltage difference between a first bitline and a second bitline in response to a first control signal and a second control signal; and an equalizer which is connected between a first supply line through which the first control signal is supplied and a second supply line through which the second control signal is supplied, and pre-charges the first bitline and the second bitline with a precharge voltage in response to an equalizing control signal, wherein the equalizer includes an equalizing enable transistor in which a source terminal is connected to the first supply line and performs equalizing in response to the equalizing control signal.

Abstract: A computing device separates a first target layer including a plurality of target patterns from an original design layout, shifts the plurality of target patterns in the first target layer based on misalignment values at positions of the plurality of target patterns to generate a second target layer, and combines the second target layer with the original design layout from which the first target layer is separated to generate a corrected design layout.

Abstract: A bit line sense amplifier of a semiconductor memory device includes: sense amplifier blocks including a PMOS driver or an NMOS driver that detects and amplifies a signal difference between a bit line and a complimentary bit line, and sequentially arranged in a bit line extending direction; column selection units that connect the bit line and a local input/output line according to a first column selection signal; complimentary column selection units that connect the complimentary bit line and a complimentary local input/output line according to a second column selection signal; column selection lines that transmit the first column selection signal to each of the column selection units; and complimentary column selection lines that transmit the second column selection signal to each of the complimentary column selection units. The column selection units and the complimentary column selection units may be disposed to be distributed between the sense amplifier blocks.

Abstract: A bitline sense amplifier including: an amplifier which is connected between a first sensing bitline and a second sensing bitline, and detects and amplifies a voltage difference between a first bitline and a second bitline in response to a first control signal and a second control signal; and an equalizer which is connected between a first supply line through which the first control signal is supplied and a second supply line through which the second control signal is supplied, and pre-charges the first bitline and the second bitline with a precharge voltage in response to an equalizing control signal, wherein the equalizer includes an equalizing enable transistor in which a source terminal is connected to the first supply line and performs equalizing in response to the equalizing control signal.

Abstract: A semiconductor memory device includes a memory bank arranged into first through nth split regions containing at least one memory cell sub-array within each split region, and first through nth global input/output (GIO) split lines electrically coupled to the first through nth split regions. First through n-lth connection control transistors are provided, which have gate terminals responsive to respective connection control signals. The first connection control transistor is configured to electrically short the first and second GIO split lines together when enabled by a corresponding connection control signal, and the n-1th connection control transistor is configured to electrically short the n-1th and nth GIO split lines together when enabled by a corresponding connection control signal. A GIO sense amplifier is provided, which is electrically coupled to the memory bank.

Abstract: A magnetic memory device includes a substrate including a cell region and a peripheral circuit region, lower contact plugs on the cell region, data storage structures on the lower contact plugs, and a peripheral interconnection structure on the peripheral circuit region. The peripheral interconnection structure includes a line portion extending in a direction parallel to a top surface of the substrate, and contact portions extending from the line portion toward the substrate. A height of each of the contact portions is less than a height of each of the lower contact plugs.

Abstract: A sense amplifier includes a bit line sense amplifier including a first transistor and a second transistor spaced apart from each other in a first direction, a second conductive line configured to electrically connect the first transistor to the second transistor and extending in the first direction and a local sense amplifier configured to at least partially overlap the second conductive line and disposed between the first transistor and the second transistor.

Abstract: A magnetic memory device includes a substrate including a cell region and a peripheral circuit region, lower contact plugs on the cell region, data storage structures on the lower contact plugs, and a peripheral interconnection structure on the peripheral circuit region. The peripheral interconnection structure includes a line portion extending in a direction parallel to a top surface of the substrate, and contact portions extending from the line portion toward the substrate. A height of each of the contact portions is less than a height of each of the lower contact plugs.

Abstract: A sub-word-line driver and semiconductor memory devices including the same are provided. The sub-word-line driver may include a word line pull-up transistor, a word line pull-down transistor, and a keeping transistor configured to maintain a word line at a specified voltage level. The sub-word-line driver may include a peripheral active region on a substrate, a first peripheral gate electrode that corresponds to a gate node of the word line pull-down transistor on the peripheral active region, a second peripheral gate electrode that corresponds to a gate node of the keeping transistor on the peripheral active region, and a first lower contact coupled to a first region of the peripheral active region. A first (VBB) voltage from the first region may be supplied to a source node of the keeping transistor.

Abstract: A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

Abstract: A sub-word-line driver and semiconductor memory devices including the same are provided. The sub-word-line driver may include a word line pull-up transistor, a word line pull-down transistor, and a keeping transistor configured to maintain a word line at a specified voltage level. The sub-word-line driver may include a peripheral active region on a substrate, a first peripheral gate electrode that corresponds to a gate node of the word line pull-down transistor on the peripheral active region, a second peripheral gate electrode that corresponds to a gate node of the keeping transistor on the peripheral active region, and a first lower contact coupled to a first region of the peripheral active region. A first (VBB) voltage from the first region may be supplied to a source node of the keeping transistor.

Abstract: A bitline sense amplifier including: an amplifier which is connected between a first sensing bitline and a second sensing bitline, and detects and amplifies a voltage difference between a first bitline and a second bitline in response to a first control signal and a second control signal; and an equalizer which is connected between a first supply line through which the first control signal is supplied and a second supply line through which the second control signal is supplied, and pre-charges the first bitline and the second bitline with a precharge voltage in response to an equalizing control signal, wherein the equalizer includes an equalizing enable transistor in which a source terminal is connected to the first supply line and performs equalizing in response to the equalizing control signal.

Abstract: A sense amplifier includes a bit line sense amplifier including a first transistor and a second transistor spaced apart from each other in a first direction, a second conductive line configured to electrically connect the first transistor to the second transistor and extending in the first direction and a local sense amplifier configured to at least partially overlap the second conductive line and disposed between the first transistor and the second transistor.

Abstract: A magnetic memory device includes a substrate including a cell region and a peripheral circuit region, lower contact plugs on the cell region, data storage structures on the lower contact plugs, and a peripheral interconnection structure on the peripheral circuit region. The peripheral interconnection structure includes a line portion extending in a direction parallel to a top surface of the substrate, and contact portions extending from the line portion toward the substrate. A height of each of the contact portions is less than a height of each of the lower contact plugs.

Abstract: A magnetic memory device includes a substrate including a cell region and a peripheral circuit region, lower contact plugs on the cell region, data storage structures on the lower contact plugs, and a peripheral interconnection structure on the peripheral circuit region. The peripheral interconnection structure includes a line portion extending in a direction parallel to a top surface of the substrate, and contact portions extending from the line portion toward the substrate. A height of each of the contact portions is less than a height of each of the lower contact plugs.

Abstract: A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

Abstract: A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

Abstract: A magnetic memory device includes a substrate including a cell region and a peripheral circuit region, lower contact plugs on the cell region, data storage structures on the lower contact plugs, and a peripheral interconnection structure on the peripheral circuit region. The peripheral interconnection structure includes a line portion extending in a direction parallel to a top surface of the substrate, and contact portions extending from the line portion toward the substrate. A height of each of the contact portions is less than a height of each of the lower contact plugs.