Abstract: A semiconductor memory device according to an embodiment of the present disclosure includes a first sub-word line driver and a second sub-word line driver. The first sub-word line driver includes a first pull-down transistor and a first keeping transistor. The second sub-word line driver includes a second pull-down transistor and a second keeping transistor. A source region of the first pull-down transistor and a source region of the second keeping transistor are disposed to share a first doping region on a semiconductor substrate, and a source region of the second pull-down transistor and a source region of the first keeping transistor are disposed to share a second doping region on the semiconductor substrate.

Abstract: A row decoder includes first and second main wordline driving circuits, which are configured to generate respective first and second driving signals onto corresponding first and second main wordlines extending adjacent to each other. In addition, a first transistor within the first main wordline driving circuit and a second transistor within the second main wordline driving circuit have the same function, but extend in different rows when viewed in a direction perpendicular to a substrate on which the first and second main wordlines are formed.

Abstract: A bitline sense amplifier including: an amplifier which is connected between a first sensing bitline and a second sensing bitline, and detects and amplifies a voltage difference between a first bitline and a second bitline in response to a first control signal and a second control signal; and an equalizer which is connected between a first supply line through which the first control signal is supplied and a second supply line through which the second control signal is supplied, and pre-charges the first bitline and the second bitline with a precharge voltage in response to an equalizing control signal, wherein the equalizer includes an equalizing enable transistor in which a source terminal is connected to the first supply line and performs equalizing in response to the equalizing control signal.

Abstract: A semiconductor device may include a first substrate, a circuit device on the first substrate, an interlayer insulating film on the circuit device, a second substrate on the interlayer insulating film, the second substrate including a first surface adjacent to the interlayer insulating film and a second surface opposite to the first surface, a device isolation trench in the second substrate and adjacent to the second surface, a device isolation structure in the device isolation trench, a through isolation film extending in the second substrate and the device isolation structure, and a through via extending into the through isolation film and electrically connected to the circuit device.

Abstract: A bitline sense amplifier including: an amplifier which is connected between a first sensing bitline and a second sensing bitline, and detects and amplifies a voltage difference between a first bitline and a second bitline in response to a first control signal and a second control signal; and an equalizer which is connected between a first supply line through which the first control signal is supplied and a second supply line through which the second control signal is supplied, and pre-charges the first bitline and the second bitline with a precharge voltage in response to an equalizing control signal, wherein the equalizer includes an equalizing enable transistor in which a source terminal is connected to the first supply line and performs equalizing in response to the equalizing control signal.

Abstract: Provided are a semiconductor memory device and a method of fabricating the same. This semiconductor memory device includes a substrate including a memory region, a dummy region, and a peripheral region arranged side by side in a first direction, and a device isolation part arranged in the substrate in the memory region and the dummy region and defining active parts, wherein the active parts include first to third active parts arranged side by side in a second direction perpendicular to the first direction in the dummy region, the first to third active parts are each elongated in a third direction intersecting the first direction and the second direction, and ends of at least two of the first to third active parts are located on a first imaginary straight line extending in the second direction.

Abstract: A method of fabricating a semiconductor device comprises: providing a substrate including a cell region and a peripheral region; stacking first and second mask layers on the substrate; patterning the second mask layer to form a first mask pattern including line patterns, wherein the line patterns extend from the cell region into a portion of the peripheral region, removing the first mask pattern on the portion; forming a first spacer layer on an upper surface of the first mask layer and on sidewalls and an upper surface of the first mask pattern on the cell region; etching the first spacer layer to form second mask patterns on the sidewalls of the first mask pattern on the cell region; removing the first mask pattern on the cell region; forming a third mask pattern on the peripheral region; and patterning the first mask layer using the second and third mask patterns.

Abstract: A semiconductor memory device includes a memory bank arranged into first through nth split regions containing at least one memory cell sub-array within each split region, and first through nth global input/output (GIO) split lines electrically coupled to the first through nth split regions. First through n-lth connection control transistors are provided, which have gate terminals responsive to respective connection control signals. The first connection control transistor is configured to electrically short the first and second GIO split lines together when enabled by a corresponding connection control signal, and the n?1th connection control transistor is configured to electrically short the n?1th and nth GIO split lines together when enabled by a corresponding connection control signal. A GIO sense amplifier is provided, which is electrically coupled to the memory bank.

Abstract: A bit line sense amplifier of a semiconductor memory device includes: sense amplifier blocks including a PMOS driver or an NMOS driver that detects and amplifies a signal difference between a bit line and a complimentary bit line, and sequentially arranged in a bit line extending direction; column selection units that connect the bit line and a local input/output line according to a first column selection signal; complimentary column selection units that connect the complimentary bit line and a complimentary local input/output line according to a second column selection signal; column selection lines that transmit the first column selection signal to each of the column selection units; and complimentary column selection lines that transmit the second column selection signal to each of the complimentary column selection units. The column selection units and the complimentary column selection units may be disposed to be distributed between the sense amplifier blocks.

Abstract: A semiconductor device including: a substrate having a portion in a cell array region and a portion in a peripheral circuit region; a peripheral circuit structure including a peripheral circuit, and peripheral circuit wiring connected to the peripheral circuit; and a cell array structure, wherein the cell array structure in the cell array region includes a plurality of bit lines extending in a first direction, a plurality of word lines extending on the plurality of bit lines in a second direction, an active pattern disposed between a first word line and a second word line, a cell landing pad connected to the active pattern, and a cell capacitor, and the cell array structure in the peripheral circuit region includes a conductive pad disposed at the same level as an end of the cell capacitor, and a lower conductive contact plug connecting the conductive pad and the peripheral circuit structure.

Abstract: A semiconductor device includes a substrate, a transistor on the substrate, a bit line structure electrically connected to the transistor, a channel layer on the bit line structure, a gate structure intersecting the bit line structure, a first conductive line electrically connecting the transistor and the bit line structure, an upper shield line overlapping the first conductive line, and side shield lines spaced apart from each other with the first conductive line interposed therebetween. The upper shield line and the side shield lines are electrically separated from the first conductive line and the bit line structure.

Abstract: A magnetic memory device includes a substrate including a cell region and a peripheral circuit region, lower contact plugs on the cell region, data storage structures on the lower contact plugs, and a peripheral interconnection structure on the peripheral circuit region. The peripheral interconnection structure includes a line portion extending in a direction parallel to a top surface of the substrate, and contact portions extending from the line portion toward the substrate. A height of each of the contact portions is less than a height of each of the lower contact plugs.

Abstract: A row decoder includes first and second main wordline driving circuits, which are configured to generate respective first and second driving signals onto corresponding first and second main wordlines extending adjacent to each other. In addition, a first transistor within the first main wordline driving circuit and a second transistor within the second main wordline driving circuit have the same function, but extend in different rows when viewed in a direction perpendicular to a substrate on which the first and second main wordlines are formed.

Abstract: A bit line sense amplifier of a semiconductor memory device includes: sense amplifier blocks including a PMOS driver or an NMOS driver that detects and amplifies a signal difference between a bit line and a complimentary bit line, and sequentially arranged in a bit line extending direction; column selection units that connect the bit line and a local input/output line according to a first column selection signal; complimentary column selection units that connect the complimentary bit line and a complimentary local input/output line according to a second column selection signal; column selection lines that transmit the first column selection signal to each of the column selection units; and complimentary column selection lines that transmit the second column selection signal to each of the complimentary column selection units. The column selection units and the complimentary column selection units may be disposed to be distributed between the sense amplifier blocks.

Abstract: A bitline sense amplifier including: an amplifier which is connected between a first sensing bitline and a second sensing bitline, and detects and amplifies a voltage difference between a first bitline and a second bitline in response to a first control signal and a second control signal; and an equalizer which is connected between a first supply line through which the first control signal is supplied and a second supply line through which the second control signal is supplied, and pre-charges the first bitline and the second bitline with a precharge voltage in response to an equalizing control signal, wherein the equalizer includes an equalizing enable transistor in which a source terminal is connected to the first supply line and performs equalizing in response to the equalizing control signal.

Abstract: A computing device separates a first target layer including a plurality of target patterns from an original design layout, shifts the plurality of target patterns in the first target layer based on misalignment values at positions of the plurality of target patterns to generate a second target layer, and combines the second target layer with the original design layout from which the first target layer is separated to generate a corrected design layout.

Abstract: A bit line sense amplifier of a semiconductor memory device includes: sense amplifier blocks including a PMOS driver or an NMOS driver that detects and amplifies a signal difference between a bit line and a complimentary bit line, and sequentially arranged in a bit line extending direction; column selection units that connect the bit line and a local input/output line according to a first column selection signal; complimentary column selection units that connect the complimentary bit line and a complimentary local input/output line according to a second column selection signal; column selection lines that transmit the first column selection signal to each of the column selection units; and complimentary column selection lines that transmit the second column selection signal to each of the complimentary column selection units. The column selection units and the complimentary column selection units may be disposed to be distributed between the sense amplifier blocks.

Abstract: A bitline sense amplifier including: an amplifier which is connected between a first sensing bitline and a second sensing bitline, and detects and amplifies a voltage difference between a first bitline and a second bitline in response to a first control signal and a second control signal; and an equalizer which is connected between a first supply line through which the first control signal is supplied and a second supply line through which the second control signal is supplied, and pre-charges the first bitline and the second bitline with a precharge voltage in response to an equalizing control signal, wherein the equalizer includes an equalizing enable transistor in which a source terminal is connected to the first supply line and performs equalizing in response to the equalizing control signal.

Abstract: A semiconductor memory device includes a memory bank arranged into first through nth split regions containing at least one memory cell sub-array within each split region, and first through nth global input/output (GIO) split lines electrically coupled to the first through nth split regions. First through n-lth connection control transistors are provided, which have gate terminals responsive to respective connection control signals. The first connection control transistor is configured to electrically short the first and second GIO split lines together when enabled by a corresponding connection control signal, and the n-1th connection control transistor is configured to electrically short the n-1th and nth GIO split lines together when enabled by a corresponding connection control signal. A GIO sense amplifier is provided, which is electrically coupled to the memory bank.

Abstract: A magnetic memory device includes a substrate including a cell region and a peripheral circuit region, lower contact plugs on the cell region, data storage structures on the lower contact plugs, and a peripheral interconnection structure on the peripheral circuit region. The peripheral interconnection structure includes a line portion extending in a direction parallel to a top surface of the substrate, and contact portions extending from the line portion toward the substrate. A height of each of the contact portions is less than a height of each of the lower contact plugs.