Abstract: A phase changing memory device, and method of making the same, that includes programmable memory material disposed between a pair of electrodes. The programmable memory material includes discrete layers of phase change material, separated by conductive interface layers, that exhibits relatively stable resistivity values over discrete ranges of crystallizing and amorphousizing thermal pulses applied thereto, for multi-bit storage. The memory material and one of the electrodes can be disposed along spacer material surfaces to form an electrical current path that narrows in width as the current path approaches the other electrode, such that electrical current passing through the current path generates heat for heating the memory material disposed between the electrodes.

Abstract: An array of floating gate memory cells, and a method of making same, where each pair of memory cells includes a pair of trenches formed into a surface of a semiconductor substrate, with a strip of the substrate disposed therebetween, a source region formed in the substrate strip, a pair of drain regions, a pair of channel regions each extending between the source region and one of the drain regions, a pair of floating gates each disposed in one of the trenches, and a pair of control gates. Each channel region has a first portion disposed in the substrate strip and extending along one of the trenches, a second portion extending underneath the one trench, a third portion extending along the one trench, and a fourth portion extending along the substrate surface and under one of the control gates.

Abstract: A method of making an array of bi-directional non-volatile memory cells in a substrate of a substantially single crystalline semiconductive material, where the material has a first conductivity type with the substrate having a substantially planar surface, comprises forming a plurality of spaced apart substantially parallel trenches in a first direction in the planar surface. Each of the trenches has a sidewall and a bottom. A region of a second conductivity type is formed in the bottom of each trench. A floating gate is formed in each trench insulated and spaced apart from the sidewall of the trench. The floating gate has a first end near the bottom and a second end furthest away from the bottom. A layer of tunneling oxide is formed about the second end of each floating gate. A layer of word region is formed on the layer of tunneling oxide. The layer of word region extends in a second direction substantially perpendicular to the first direction.

Abstract: A multi-bit Read Only Memory (ROM) cell has a semiconductor substrate of a first conductivity type with a first concentration. A first and second regions of a second conductivity type spaced apart from one another are in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. The ROM cell has one of a plurality of N possible states, where N is greater than 2. The possible states of the ROM cell are determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost.

Abstract: A method of making an array of bi-directional non-volatile memory cells in a substrate of a substantially single crystalline semiconductive material, where the material has a first conductivity type with the substrate having a substantially planar surface, comprises forming a plurality of spaced apart substantially parallel trenches in a first direction in the planar surface. Each of the trenches has a sidewall and a bottom. A region of a second conductivity type is formed in the bottom of each trench. A floating gate is formed in each trench insulated and spaced apart from the sidewall of the trench. The floating gate has a first end near the bottom and a second end furthest away from the bottom. A layer of tunneling oxide is formed about the second end of each floating gate. A layer of word region is formed on the layer of tunneling oxide. The layer of word region extends in a second direction substantially perpendicular to the first direction.

Abstract: A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost.

Abstract: A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost.

Abstract: A phase changing memory device, and method of making the same, that includes contact holes formed in insulation material that extend down to and exposes source regions for adjacent FET transistors. Spacer material is disposed in the holes with surfaces that define openings each having a width that narrows along a depth of the opening. Lower electrodes are disposed in the holes. A layer of phase change memory material is disposed along the spacer material surfaces and along at least a portion of the lower electrodes. Upper electrodes are formed in the openings and on the phase change memory material layer. For each contact hole, the upper electrode and phase change memory material layer form an electrical current path that narrows in width as the current path approaches the lower electrode, such that electrical current passing through the current path generates heat for heating the phase change memory material disposed between the upper and lower electrodes.

Abstract: An integrated circuit plasma processing system, apparatus and method for reclaiming material, such as a plasma precursor and potentially useful components among their byproducts, from plasma-enhanced exhaust of a plasma process chamber for subsequent reuse in the chamber. The apparatus provides a recycle feedback loop for a plasma process chamber that provides the high purity materials necessary for microelectronic applications. Since the apparatus is in-situ, no byproducts that are not already present are possible. Accordingly, the apparatus guarantees purity of the recycled material. In addition to cost savings, the invention provides an environmentally friendly plasma process chamber and apparatus with very little production of waste.

Abstract: A nonvolatile memory cell having a floating gate for the storage of charges thereon has a control gate and a separate erase gate. The cell is programmed by hot channel electron injection and is erased by poly to poly Fowler-Nordheim tunneling. A method for making an array of unidirectional cells in a planar substrate, as well as an array of bidirectional cells in a substrate having a trench, is disclosed. An array of such cells and a method of making such an array is also disclosed.

Abstract: A nonvolatile reprogrammable switch for use in a PLD or FPGA has a nonvolatile memory cell connected to the gate of an MOS transistor with the terminals of the MOS transistor connected to the source of the signal and to the circuit. The nonvolatile memory cell is of a split gate type having a first region and a second region, with a channel therebetween. The cell has a floating gate positioned over a first portion of the channel, which is adjacent to the first region and a control gate positioned over a second portion of the channel, which is adjacent to the second region. The second region is connected to the gate of the MOS transistor. The cell is programmed by injecting electrons from the channel onto the floating gate by hot electron injection mechanism. The cell is erased by Fowler-Nordheim tunneling of the electrons from the floating gate to the control gate. As a result, no high voltage is ever applied to the second region during program or erase.

Abstract: A buried bit line read/program non-volatile memory cell and array is capable of achieving high density. The cell and array is made in a semiconductor substrate which has a plurality of spaced apart trenches, with a planar surface between the trenches. Each trench has a side wall and a bottom wall. Each memory cell has a floating gate for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having two portions. One of the source/drain regions is in the bottom wall of the trench. The floating gate is in the trench and is is over a first portion of the channel and is spaced apart from the side wall of the trench. A gate electrode controls the conduction of the channel in the second portion, which is in the planar surface of the substrate. The other source/drain region is in the substrate in the planar surface of the substrate.

Abstract: A non-volatile memory cell has a single crystalline semiconductive material, such as single crystalline silicon, of a first conductivity type. A first and a second region each of a second conductivity type, different from the first conductivity type, spaced apart from one another is formed in the semiconductive material. A channel region, having a first portion, and a second portion, connects the first and second regions for the conduction of charges. A dielectric is on the channel region. A floating gate, which can be conductive or non-conductive, is on the dielectric, spaced apart from the first portion of the channel region. The first portion of the channel region is adjacent to the first region, with the first floating gate having generally a triangular shape. The floating gate is formed in a cavity. A gate electrode is capacitively coupled to the first floating gate, and is spaced apart from the second portion of the channel region.

Abstract: A method of forming a floating gate memory cell array, and the array formed thereby, wherein a trench is formed into the surface of a semiconductor substrate. The source and drain regions are formed underneath the trench and along the substrate surface, respectively, with a non-linear channel region therebetween. The floating gate has a lower portion disposed in the trench and an upper portion disposed above the substrate surface and having a lateral protrusion extending parallel to the substrate surface. The lateral protrusion is formed by etching a cavity into an exposed end of a sacrificial layer and filling it with polysilicon. The control gate is formed about the lateral protrusion and is insulated therefrom. The trench sidewall meets the substrate surface at an acute angle to form a sharp edge that points toward the floating gate and in a direction opposite to that of the lateral protrusion.

Abstract: A phase change memory device, and method of making the same, that includes contact holes formed in insulation material that extend down to and exposes source regions for adjacent FET transistors. Spacer material is disposed in the holes with surfaces that define openings each having a width that narrows along a depth of the opening. Lower electrodes are disposed in the holes. A layer of phase change material is disposed along the spacer material surfaces and along at least a portion of the lower electrodes. Upper electrodes are formed in the openings and on the phase change material layer. Voids are formed into the spacer material to impede heat from the phase change material from conducting through the insulation material. For each contact hole, the upper electrode and phase change material layer form an electrical current path that narrows in width as the current path approaches the lower electrode.

Abstract: A system and method for aligning a wafer in an exposure apparatus includes a holder adapted to hold a wafer (the wafer includes alignment marks), a coarse alignment system, and a fine alignment system having a higher precision than the coarse alignment system. The fine alignment system includes multiple optical detectors. Each of the optical detectors is positioned to detect a corresponding alignment mark on the wafer. An alignment processor is connected to and controls the optical detectors and the holder. The optical detectors are controlled by the alignment processor to simultaneously detect the alignment marks in parallel operations. Further, the alignment processor simultaneously processes signals from the optical detectors in parallel operations.

Abstract: A nonvolatile reprogrammable switch for use in a PLD or FPGA has a nonvolatile memory cell connected to the gate of an MOS transistor, which is in a well, with the terminals of the MOS transistor connected to the source of the signal and to the circuit. The nonvolatile memory cell is of a split gate type having a first region and a second region, with a channel therebetween. The cell has a floating gate positioned over a first portion of the channel, which is adjacent to the first region and a control gate positioned over a second portion of the channel, which is adjacent to the second region. The second region is connected to the gate of the MOS transistor. The cell is programmed by injecting electrons from the channel onto the floating gate by hot electron injection mechanism. The cell is erased by Fowler-Nordheim tunneling of the electrons from the floating gate to the control gate. As a result, no high voltage is ever applied to the second region during program or erase.

Abstract: A non-volatile memory cell has a single crystalline semiconductive material, such as single crystalline silicon, of a first conductivity type. A first and a second region each of a second conductivity type, different from the first conductivity type, spaced apart from one another is formed in the semiconductive material. A channel region, having a first portion, and a second portion, connects the first and second regions for the conduction of charges. A dielectric is on the channel region. A floating gate, which can be conductive or non-conductive, is on the dielectric, spaced apart from the first portion of the channel region. The first portion of the channel region is adjacent to the first region, with the first floating gate having generally a triangular shape. The floating gate is formed in a cavity. A gate electrode is capacitively coupled to the first floating gate, and is spaced apart from the second portion of the channel region.

Abstract: A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. An independently controllable control gate is insulated from each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate.

Abstract: A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. A control gate is connected to each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate.