Abstract: A patterned buried insulator is formed beneath the source and drain by forming a mask over the body area and implanting a dose of n or p type ions in the areas where the source and drains will be formed, then etching the STI and etching out the implanted area. A light oxidation is followed by a conformal oxide deposition in the STI and also in the etched area, thereby forming the buried oxide only where desired.

Abstract: A patterned buried insulator is formed beneath the source and drain by forming a mask over the body area and implanting a dose of n or p type ions in the areas where the source and drains will be formed, then etching the STI and etching out the implanted area. A light oxidation is followed by a conformal oxide deposition in the STI and also in the etched area, thereby forming the buried oxide only where desired.

Abstract: A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory region and the logic region, removing the protective layer over the logic region to expose the substrate, and forming the logic device in the logic region. Cobalt or titanium metal is applied over all horizontal surfaces in the logic region and annealed, forming a salicide where the metal rests over silicon or polysilicon regions, and any unreacted metal is removed. An uppermost nitride layer is then applied over both the memory and logic regions and is then covered with a filler in the logic region. Chip structures resulting from various embodiments of the process are also disclosed.

Abstract: Shallow trench isolation is combined with optional deep trenches that are self-aligned with the shallow trenches, at the corners of the shallow trenches, and have a deep trench width that is controlled by the thickness of a temporary sidewall deposited in the interior of the shallow trench and is limited by the sidewall deposition thickness of the deep trench fill.

Abstract: A pair of transistors sharing a common electrodes e.g. a bitline in a DRAM array, has a self-aligned contact to the bitline in which the transistor gate stack has only a poly layer with a nitride cover; the aperture for the bitline contact is time-etched to penetrate only between the gates and not reach the silicon substrate; exposed nitride shoulders of the gate are etched to expose the poly; the remainder of the interlayer dielectric is removed by a selective etch; the exposed poly is re-oxidized to protect the gates; and the aperture bottom is cleaned; so that the thick gate stack of a DRAM is dispensed with in order to improve uniformity of line width across the chip beyond what the DRAM technique can deliver.

Abstract: Source and drain regions of field effect transistors are fabricated with an electrically insulating layer formed thereunder so as to reduce junction capacitance between each and a semiconductor body in which the regions are formed. Shallow trench isolation partially surrounds each transistor so as to further electrically isolate the source and drain regions from the semiconductor body. Typically for a single transistor only one surface of each drain and source region make direct contact to the semiconductor body and these surfaces are on opposite sides of a channel region of each transistor. One method of fabrication of the source and drain regions is to form an isolating isolation region around active areas in which a transistor is to be formed in a semiconductor body. Trenches separated by portions of the body are then formed in the active areas in which transistors are to be formed. On bottom surfaces of the trenches are formed an electrically insulating layer.

Abstract: A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory region and the logic region, removing the protective layer over the logic region to expose the substrate, and forming the logic device in the logic region. Cobalt or titanium metal is applied over all horizontal surfaces in the logic region and annealed, forming a salicide where the metal rests over silicon or polysilicon regions, and any unreacted metal is removed. An uppermost nitride layer is then applied over both the memory and logic regions and is then covered with a filler in the logic region. Chip structures resulting from various embodiments of the process are also disclosed.

Abstract: The difficulty of etching noble metals in ferroelectric capacitors is eliminated by a damascene process that employs chemical-mechanical polishing to remove the unwanted material, resulting in a lower electrode formed in an aperture in a dielectric, having a flat central portion and a wall extending from the central portion to the top surface of the surrounding dielectric; and an upper electrode formed in a two-level aperture, so that the upper electrode structure has a flat central portion, a first vertical wall extending from the central portion to a rim surrounding the central portion and extending over the wall of the lower electrode, and a second vertical wall extending from the rim to the top surface of a surrounding dielectric.

Abstract: An SRAM cell consisting of a cross coupled transistors, a pair of transfer gate transistors and, a pair of load resistors, loading the cross-coupled transistors. Where soft error immunity is desired, the SRAM cell has a buried oxide layer isolating the devices from the silicon substrate. The load resistor is integrated into a contact stud, connecting a diffusion region of the SRAM cell to a power supply. An opening, in an insulating layer overlying the substrate and in contact with parts of the transistors including some diffusion regions, exposes a selected diffusion region of the SRAM cell. The contact stud with an integral resistor, consists of a core of a conductive material, and a highly resistive thin layer between the conducting core and the sides of the opening in the insulator and the selected contact areas. The conductive layer and the resistive layer are nearly planar with the top of the insulating layer.

Abstract: The present invention provides a method of global stress modification which results in reducing number of dislocations in an epitaxially grown semiconducting device layer on a semiconductor substrate where the device layer and the substrate have a lattice mismatch. The invention teaches a method of imparting a convex curvature to the substrate by removing layer(s) of thin film from or adding layers of thin film to the back side of the substrate, so as to achieve a reduced dislocation density in the device layer.

Abstract: A method for forming a capacitor on a substrate having a contact below a top layer including the steps of:Spinning on a layer of photoresist material. Exposing the photoresist to light to establish a standing wave pattern to fix prominences of photoresist separated by separation areas. Each prominence extends a prominence height from the top layer to a top. Developing the photoresist to fix an erose face on each prominence, each face extending from the top layer to the top. Depositing a first oxide intermediate prominences to effect accumulation of the first oxide to an oxide height at least equal to the prominence height. Etching the first oxide to expose each top. Dissolving the photoresist to uncover oxide mandrels. Each mandrel extends a mandrel height from the top layer to a mandrel top; each mandrel has an erose mandrel face intermediate the top layer and the mandrel top. Etching the top layer to expose the contact.

Abstract: Integrated circuit structures of sub-lithography dimensions are formed by conformal deposition of alternating layers of materials having differing etch rates within an aperture over a body of material to be etched. One of the materials in the alternating layers is then selectively and preferentially etched to form a mask through which etching can be performed on the body of material to be etched. This technique is particularly suited to the formation of structurally robust capacitors for memory cells which have greatly increased plate area, resulting in increased capacitance, while maintaining a small footprint for the capacitor structure.