Abstract: An apparatus is provided for handling workpieces, such as semiconductor wafers, during semiconductor processing. The apparatus includes a wafer platen having a plurality of channels each extending from a top surface to a bottom surface of the wafer platen, a plurality of lift pins in alignment with the channels, and a mechanism for engaging the lift pins in a loading position of the workpiece, a clamping position of the workpiece so that desired semiconductor processes may be performed to the workpiece, and a lift off position for removing the workpiece from the wafer platen after the semiconductor processes are completed. The mechanism places the lift pins below the surface of the wafer platen in the load position and then raises the lift pins to a first predetermined distance above the surface of the wafer platen in the clamp position such that the first predetermined distance allows the workpiece to be clamped to the wafer platen.

Abstract: A Faraday dose and uniformity monitor can include a magnetically suppressed annular Faraday cup surrounding a target wafer. A narrow aperture can reduce discharges within Faraday cup opening. The annular Faraday cup can have a continuous cross section to eliminate discharges due to breaks. A plurality of annular Faraday cups at different radii can independently measure current density to monitor changes in plasma uniformity. The magnetic suppression field can be configured to have a very rapid decrease in field strength with distance to minimize plasma and implant perturbations and can include both radial and azimuthal components, or primarily azimuthal components. The azimuthal field component can be generated by multiple vertically oriented magnets of alternating polarity, or by the use of a magnetic field coil. In addition, dose electronics can provide integration of pulsed current at high voltage, and can convert the integrated charge to a series of light pulses coupled optically to a dose controller.

Abstract: An apparatus is provided for handling workpieces, such as semiconductor wafers, during semiconductor processing. The apparatus includes a wafer platen having a plurality of channels each extending from a top surface to a bottom surface of the wafer platen, a plurality of lift pins in alignment with the channels, and a mechanism for engaging the lift pins in a loading position of the workpiece, a clamping position of the workpiece so that desired semiconductor processes may be performed to the workpiece, and a lift off position for removing the workpiece from the wafer platen after the semiconductor processes are completed. The mechanism places the lift pins below the surface of the wafer platen in the load position and then raises the lift pins to a first predetermined distance above the surface of the wafer platen in the clamp position such that the first predetermined distance allows the workpiece to be clamped to the wafer platen.

Abstract: Methods and apparatus are provided for monitoring plasma parameters in plasma doping systems. A plasma doping system includes a plasma doping chamber, a platen located in the plasma doping chamber for supporting a workpiece, an anode spaced from the platen in the plasma doping chamber, a process gas source coupled to the plasma doping chamber, a pulse source for applying pulses between the platen and the anode, and a plasma monitor. A plasma containing ions of the process gas is produced in a plasma discharge region between the anode and the platen. The pulses accelerate ions from the plasma into the workpiece. The plasma monitor may include a sensing device which senses a spatial distribution of a plasma parameter, such as plasma density, that is indicative of dose distribution of ions implanted into the workpiece.

Abstract: A method for forming a shallow junction in a semiconductor wafer may include amorphizing the wafer to obtain a depth of end-of-range (EOR) defects that is smaller than a desired junction depth in a range of about 13 nm to about 50 nm, implanting a dopant material into the wafer at a selected dose and energy to produce the desired junction depth, and activating the dopant material by thermal processing of the semiconductor wafer at a selected temperature for a selected time consistent with low-temperature solid phase epitaxy (SPE) annealing to form the shallow junction. The control of the EOR depth through a preamorphizing implant to less than the junction depth provides for a low leakage junction and the low-temperature SPE anneal prevents diffusion of the dopant beyond the desired junction depth.