Abstract: A transparent heating structure includes a substrate and a pattern portion. The substrate is transparent to visible light. The pattern portion is disposed on the substrate, and is configured to transmit communication frequency bands and to be heated. The pattern portion has a plurality of cells disposed on the substrate, and each of the cells has a plurality of unit grids having a slot.

Abstract: Disclosed are an improved guide device capable of being easily replaced for damage, and a detector having the same. The guide device includes a first plate configured to have a plurality of grooves disposed in one surface thereof; and a second plate configured to be in contact with the first plate, wherein the second plate is in contact with the first plate to separate a plurality of channels, wherein the first plate is configured so that the plurality of microdroplets pass through any one of the plurality of channels, the fluid passes through channels facing each other among the plurality of flow channels, and the microdroplets are regularly spaced apart by the fluid that is discharged from the channels facing each other.

Abstract: A method of determining a counterfeit fingerprint by a system for determining a counterfeit fingerprint that includes an internal light source and an external light source, comprising: extracting a first fingerprint area of a first fingerprint image obtained from a light signal of the internal light source when a target object's fingerprint comes in contact with a fingerprint contact surface of the system for determining a counterfeit fingerprint; extracting a second fingerprint area of a second fingerprint image obtained from a light signal of the external light source based on the first fingerprint area; and inputting the first fingerprint area and the second fingerprint area into a pre-trained neural network of the system for determining a counterfeit fingerprint to output a result of determining whether the fingerprint is counterfeit.

Abstract: Disclosed herein are a metastructure having a zero elastic modulus zone, which can experience constant stress in a predetermined strain zone, and a method for designing the same. The metastructure includes a first unit and a second unit, wherein the first unit has a structure capable of buckling and has a stress-strain relation having a zone corresponding to a negative elastic modulus, the second unit is disposed adjacent to the first unit and has a stress-strain relation having a zone corresponding to a positive elastic modulus, and the metastructure has zero elastic modulus in a predetermined target strain zone through synthesis of the negative elastic modulus of the first unit with the positive elastic modulus of the second unit.

Abstract: A display device includes: a substrate including a display area having a plurality of pixel areas and a non-display area surrounding at least one side of the display area; a light-blocking layer disposed on a first surface of the substrate and including light transmissive areas to allow incident light to pass therethrough; a circuit-element layer disposed on the light-blocking layer and including a plurality of conductive layers; a light-emitting element layer disposed on the circuit-element layer and including light-emitting elements; and a sensor layer disposed on a second surface of the substrate opposing the first surface to sense the light passing through the light transmissive areas. The light-blocking layer is electrically coupled to at least one of the plurality of conductive layers.

Abstract: Provided are a beam splitter using a multiple refractive index layer, which enables high magnification measurement by transmitting infrared light and reflecting visible light, and a defective element detection device including the same. The beam splitter includes a multiple refractive index layer and a base layer. The multiple refractive index layer is configured to reflect first light and transmit second light having a wavelength longer than a wavelength of the first light. The base layer is provided on one side of the multiple refractive index layer and configured to transmit the second light transmitted through the multiple refractive index layer. The multiple refractive index layer includes a first refractive index layer having a first refractive index and a second refractive index layer having a second refractive index less than the first refractive index.

Abstract: The present invention relates to a Corynebacterium glutamicum mutant strain having enhanced L-lysine productivity and a method of producing L-lysine using the same. The Corynebacterium glutamicum mutant strain is able to produce L-lysine in an improved yield as a result of improving the activity of glyceraldehyde 3-phosphate dehydrogenase by mutagenesis of amino acids in the gene encoding glyceraldehyde 3-phosphate dehydrogenase.

Abstract: A system and method of designing an integrated circuit (IC) by considering a local layout effect are provided. The method of designing an IC may place instances of pre-placement cells so as to decrease occurrence of a local layout effect (LLE) causing structure. The method may extract a context of an instance from a peripheral layout of each of the placed instances to estimate an LLE of the instance, thereby analyzing a performance of the IC.

Abstract: An integrated circuit (IC) including a first synchronous circuit configured to operate in synchronization with a clock signal is provided. The first synchronous circuit includes a selector including a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, and a third input terminal configured to receive a scan enable signal indicating one of a scan test mode and a function operation mode and a latch unit configured to operate as a flip-flop outputting a first output signal corresponding to the first input signal in the scan test mode and to operate as a latch outputting a second output signal corresponding to the second input signal in the function operation mode.

Abstract: An integrated circuit (IC) including a first synchronous circuit configured to operate in synchronization with a clock signal is provided. The first synchronous circuit includes a selector including a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, and a third input terminal configured to receive a scan enable signal indicating one of a scan test mode and a function operation mode and a latch unit configured to operate as a flip-flop outputting a first output signal corresponding to the first input signal in the scan test mode and to operate as a latch outputting a second output signal corresponding to the second input signal in the function operation mode.

Abstract: A system and method of designing an integrated circuit (IC) by considering a local layout effect are provided. The method of designing an IC may place instances of pre-placement cells so as to decrease occurrence of a local layout effect (LLE) causing structure. The method may extract a context of an instance from a peripheral layout of each of the placed instances to estimate an LLE of the instance, thereby analyzing a performance of the IC.

Abstract: A method for managing network access is provided. The method includes determining whether there is a network connection request from at least one application, checking at least one attribute information item of the application, determining an access point name (APN) corresponding to the application based on the at least one attribute information item, and transmitting and receiving data of the application to/from a network using the determined APN.

Abstract: A method for managing network access is provided. The method includes determining whether there is a network connection request from at least one application, checking at least one attribute information item of the application, determining an access point name (APN) corresponding to the application based on the at least one attribute information item, and transmitting and receiving data of the application to/from a network using the determined APN.

Abstract: Example embodiments relate to a method performed by an apparatus for analyzing time of a semiconductor chip. The method may include defining a netlist, defining time delays of devices defined in the netlist, performing a normality test using the time delays, judging a p-value based on the normality test, and determining a time delay of the semiconductor chip.

Abstract: A mobile terminal includes a front body, a rear body, and a slide module connecting the front body to the rear body such that the front body is slidable with respect to the rear body, the slide module including a first slide member fixed to a front surface of the rear body and having a rail unit at both sides of the rear body, the rail unit having a specific length corresponding to a slide stroke of the front body; and a second slide member fixed to a rear surface of the front body and having a moving guide constrained to the rail unit at both sides of the rear body and slidably moved along the rail unit, in which the moving guide protrudes toward the rear body in order to receive the rail unit and cover the rail unit.

Abstract: Example embodiments relate to a method performed by an apparatus for analyzing time of a semiconductor chip. The method may include defining a netlist, defining time delays of devices defined in the netlist, performing a normality test using the time delays, judging a p-value based on the normality test, and determining a time delay of the semiconductor chip.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate; a dummy pattern extending in one direction on the semiconductor substrate; a junction region electrically connecting the dummy pattern to the semiconductor substrate; and a voltage applying unit that is configured to apply a bias voltage to the dummy pattern.

Abstract: In a method of estimating a leakage current in a semiconductor device, a chip including a plurality of cells is divided into segments by a grid model. Spatial correlation is determined as spatial correlation between process parameters concerned with the leakage currents in each of the cells. A virtual cell leakage characteristic function of a cell is generated by arithmetically operating actual leakage characteristic functions. A segment leakage characteristic function of a segment is generated by arithmetically operating the virtual cell leakage characteristic functions of all cells in the segment. Then, a full chip leakage characteristic function of the chip is generated by statistically operating the segment leakage characteristic functions of all segments in the chip. Accordingly, computational loads of Wilkinson's method for generating the full chip leakage characteristic function can remarkably be reduced.

Abstract: A circuit having an active clock shielding structure includes a logic circuit that receives a clock signal and performs a logic operation based on the clock signal, a power gating circuit that switches a mode of the logic circuit between an active mode and an sleep mode based on a power gating signal, a clock signal transmission line that transmits the clock signal to the logic circuit, and at least one power gating signal transmission line that transmits the power gating signal to the power gating circuit and functions as a shielding line pair with the clock signal transmission line.

Abstract: A power gating circuit includes a logic circuit, a switching element and a retention flip-flop. The logic circuit is coupled between a first power rail and a virtual power rail. The switching element selectively couples the virtual power rail to a second power rail in response to a mode control signal indicating an active mode or a standby mode. The retention flip-flop selectively performs a flip-flop operation or a data retention operation in response to a voltage of the virtual power rail.