Patents by Inventor Bong-Jin Kuh
Bong-Jin Kuh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8970039Abstract: A semiconductor device includes a plurality of electrode structures perpendicularly extending on a substrate, and at least one support unit extending between the plurality of electrode structures. The support unit includes at least one support layer including a noncrystalline metal oxide contacting a part of the plurality of electrode structures. Related devices and fabrication methods are also discussed.Type: GrantFiled: December 6, 2012Date of Patent: March 3, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Bong-jin Kuh, Sang-ryol Yang, Soon-wook Jung, Young-sub You, Byung-hong Chung, Han-mei Choi, Jong-sung Lim
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Publication number: 20140357062Abstract: A method of fabricating a semiconductor device, the method including forming a trench on a substrate; forming an insulating layer pattern within the trench; depositing an amorphous material on the substrate and the insulating layer pattern; planarizing the amorphous material; removing a portion of the amorphous material, the removed portion of the amorphous material being on an area of the substrate where the trench has been formed; crystallizing remaining portions of the amorphous material into a single crystal material; and planarizing the single crystal material.Type: ApplicationFiled: May 29, 2014Publication date: December 4, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joong-Han SHIN, Bong-Jin KUH, Tae-Gon KIM, Han-Mei CHOI, Jeong-Meung KIM
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Publication number: 20140256117Abstract: A method of forming an epitaxial layer includes forming a plurality of first insulation patterns in a substrate, the plurality of first insulation patterns spaced apart from each other, forming first epitaxial patterns on the plurality of first insulation patterns, forming second insulation patterns between the plurality of first insulation patterns to contact the plurality of first insulation patterns, and forming second epitaxial patterns on the second insulation patterns and between the first epitaxial patterns to contact the first epitaxial patterns, the first epitaxial patterns and the second epitaxial patterns forming a single epitaxial layer.Type: ApplicationFiled: December 19, 2013Publication date: September 11, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Joong-han SHIN, Bong-jin KUH, Ki-chul KIM, Jeong-meung KIM, Eun-ha LEE, Jong-sung LIM, Han-mei CHOI
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Patent number: 8815697Abstract: Provided is a method of manufacturing a semiconductor device having a capacitor. The method includes forming a composite layer, including sequentially stacking on a substrate alternating layers of first through nth sacrificial layers and first through nth supporting layers. A plurality of openings that penetrate the composite layer are formed. A lower electrode is formed in the plurality of openings. At least portions of the first through nth sacrificial layers are removed to define a support structure for the lower electrode extending between adjacent ones of the plurality of openings and the lower electrode formed therein, the support structure including the first through nth supporting layers and a gap region between adjacent ones of the first through nth supporting layers where the first through nth sacrificial layers have been removed. A dielectric layer is formed on the lower electrode and an upper electrode is formed on the dielectric layer.Type: GrantFiled: May 23, 2012Date of Patent: August 26, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Ho Yoon, Bong-Jin Kuh, Ki-Chul Kim, Gyung-Jin Min, Tae-Jin Park, Sang-Ryol Yang, Jung-Min Oh, Sang-Yoon Woo, Young-Sub Yoo, Ji-Eun Lee, Jong-Sung Lim, Yong-Moon Jang, Han-Mei Choi, Je-Woo Han
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Publication number: 20140209858Abstract: A nano-structure semiconductor light emitting device includes a base layer formed of a first conductivity type semiconductor, and a first insulating layer disposed on the base layer and having a plurality of first openings exposing partial regions of the base layer. A plurality of nanocores is disposed in the exposed regions of the base layer and formed of the first conductivity-type semiconductor. An active layer is disposed on surfaces of the plurality of nanocores and positioned above the first insulating layer. A second insulating layer is disposed on the first insulating layer and has a plurality of second openings surrounding the plurality of nanocores and the active layer disposed on the surfaces of the plurality of nanocores. A second conductivity-type semiconductor layer is disposed on the surface of the active layer positioned to be above the second insulating layer.Type: ApplicationFiled: January 27, 2014Publication date: July 31, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Nam Goo Cha, Bong Jin Kuh, Han Mei Choi
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Publication number: 20140193967Abstract: In a method of forming an epitaxial layer, an etching gas may be decomposed to form decomposed etching gases. A source gas may be decomposed to form decomposed source gases. The decomposed source gases may be applied to a substrate to form the epitaxial layer on the substrate. A portion of the epitaxial layer on a specific region of the substrate may be etched using the decomposed etching gases. Before the etching gas is introduced into the reaction chamber, the etching gas may be previously decomposed. The decomposed etching gases may then be introduced into the reaction chamber to etch the epitaxial layer on the substrate. As a result, the epitaxial layer on the substrate may have a uniform distribution.Type: ApplicationFiled: January 10, 2014Publication date: July 10, 2014Applicants: Kookje Electric Korea Co., Ltd., Samsung Electronics Co., Ltd.Inventors: Sung-Ho KANG, Bong-Jin KUH, Yong-Kyu JOO, Sung-Ho HEO, Hee-Seok KIM, Yong-Sung PARK
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Publication number: 20140144380Abstract: A gas supply pipe and a chemical vapor deposition (CVD) apparatus including the gas supply pipe. The gas supply pipe includes: a first pipe connected to a gas storage apparatus via a gas supply line to supply a reacting gas into a reacting furnace; and a second pipe thermally contacting the first pipe to cool the first pipe, wherein a first end of the second pipe is connected to a cooling medium supplying unit via a cooling medium line such that a cooling medium circulates inside the second pipe, and a second, opposite end of the second pipe is connected to a cooling medium collecting unit.Type: ApplicationFiled: November 28, 2012Publication date: May 29, 2014Inventors: Sung-ho Kang, Bong-jin Kuh, Ki-chul Kim, Jin-kwon Bok, Yong-kyu Joo, Sang-cheol Ha
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Publication number: 20140138794Abstract: A semiconductor device includes a plurality of lower electrodes having a vertical length greater than a horizontal width on a substrate, a supporter disposed between the lower electrodes, an upper electrode disposed on the lower electrodes, and a capacitor dielectric layer disposed between the lower electrodes and the upper electrode. The supporter includes a first element, a second element, and oxygen, an oxide of the second element has a higher band gap energy than an oxide of the first element, and the content of the second element in the supporter is from about 10 at % to 90 at %.Type: ApplicationFiled: October 29, 2013Publication date: May 22, 2014Inventors: Hyun-Jeong YANG, Soon-Wook JUNG, Bong-Jin KUH, Wan-Don KIM, Byung-Hong CHUNG, Yong-Suk TAK
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Patent number: 8617950Abstract: A capacitor is fabricated by forming a mold layer of a silicon based material that is not an oxide of silicon, e.g., polysilicon or doped polysilicon, on a substrate, forming an opening through the mold layer, forming a barrier layer pattern along the sides of the opening, subsequently forming a lower electrode in the opening, then removing the mold layer and the barrier layer pattern, and finally sequentially forming dielectric layer and an upper electrode on the lower electrode.Type: GrantFiled: April 3, 2012Date of Patent: December 31, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Bong Jin Kuh, Jong Cheol Lee, Yong Suk Tak, Young Sub You, Kyu Ho Cho, Jong Sung Lim
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Patent number: 8513051Abstract: Phase-changeable memory devices include a lower electrode electrically connected to an impurity region of a transistor in a substrate and a programming layer pattern including a first phase-changeable material on the lower electrode. An adiabatic layer pattern including a material having a lower thermal conductivity than the first phase-changeable material is on the programming layer pattern and an upper electrode is on the adiabatic layer pattern.Type: GrantFiled: February 19, 2010Date of Patent: August 20, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Ho Ha, Bong-Jin Kuh, Ji-Hye Yi, Jun-Soo Bae
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Patent number: 8492251Abstract: A thin layer structure includes a substrate, a blocking pattern that exposes part of an upper surface of the substrate, and a single crystalline semiconductor layer on the part of the upper surface of the substrate exposed by the pattern and in which all outer surfaces of the single crystalline semiconductor layer have a <100> crystallographic orientation. The thin layer structure is formed by an SEG process in which the temperature is controlled to prevent migration of atoms in directions towards the central portion of the upper surface of the substrate. Thus, sidewall surfaces of the layer will not be constituted by facets.Type: GrantFiled: August 28, 2012Date of Patent: July 23, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Hoon Kang, Bong-Jin Kuh, Tae-Gon Kim, Han-Mei Choi, Ki-Chul Kim, Eun-Young Jo
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Patent number: 8445354Abstract: A method of manufacturing a phase-change memory device comprises forming a contact region on a substrate, forming a lower electrode electrically connected to the contact region, forming a phase-change material layer on the lower electrode using a chalcogenide compound target including carbon and metal, or carbon, nitrogen and metal, and forming an upper electrode on the phase-change material layer.Type: GrantFiled: February 8, 2012Date of Patent: May 21, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Ho Ha, Bong-Jin Kuh, Han-Bong Ko, Doo-Hwan Park, Sang-Wook Lim, Hee-Ju Shin
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Publication number: 20130115760Abstract: A thin layer structure includes a substrate, a blocking pattern that exposes part of an upper surface of the substrate, and a single crystalline semiconductor layer on the part of the upper surface of the substrate exposed by the pattern and in which all outer surfaces of the single crystalline semiconductor layer have a <100> crystallographic orientation. The thin layer structure is formed by an SEG process in which the temperature is controlled to prevent migration of atoms in directions towards the central portion of the upper surface of the substrate. Thus, sidewall surfaces of the layer will not be constituted by facets.Type: ApplicationFiled: August 28, 2012Publication date: May 9, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: JONG-HOON KANG, BONG-JIN KUH, TAE-GON KIM, HAN-MEI CHOI, KI-CHUL KIM, EUN-YOUNG JO
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Publication number: 20130005110Abstract: Provided is a method of manufacturing a semiconductor device having a capacitor. The method includes forming a composite layer, including sequentially stacking on a substrate alternating layers of first through nth sacrificial layers and first through nth supporting layers. A plurality of openings that penetrate the composite layer are formed. A lower electrode is formed in the plurality of openings. At least portions of the first through nth sacrificial layers are removed to define a support structure for the lower electrode extending between adjacent ones of the plurality of openings and the lower electrode formed therein, the support structure including the first through nth supporting layers and a gap region between adjacent ones of the first through nth supporting layers where the first through nth sacrificial layers have been removed. A dielectric layer is formed on the lower electrode and an upper electrode is formed on the dielectric layer.Type: ApplicationFiled: May 23, 2012Publication date: January 3, 2013Inventors: Jun-Ho Yoon, Bong-Jin Kuh, Ki-Chul Kim, Gyung-Jin Min, Tae-Jin Park, Sang-Ryol Yang, Jung-Min Oh, Sang-Yoon Woo, Young-Sub Yoo, Ji-Eun Lee, Jong-Sung Lim, Yong-Moon Jang, Han-Mei Choi, Je-Woo Han
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Publication number: 20120264271Abstract: A capacitor is fabricated by forming a mold layer of a silicon based material that is not an oxide of silicon, e.g., polysilicon or doped polysilicon, on a substrate, forming an opening through the mold layer, forming a barrier layer pattern along the sides of the opening, subsequently forming a lower electrode in the opening, then removing the mold layer and the barrier layer pattern, and finally sequentially forming dielectric layer and an upper electrode on the lower electrode.Type: ApplicationFiled: April 3, 2012Publication date: October 18, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: BONG JIN KUH, JONG-CHEOL LEE, YONG-SUK TAK, YOUNG-SUB YOU, KYU-HO CHO, JONG-SUNG LIM
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Publication number: 20120142161Abstract: A method of manufacturing a phase-change memory device comprises forming a contact region on a substrate, forming a lower electrode electrically connected to the contact region, forming a phase-change material layer on the lower electrode using a chalcogenide compound target including carbon and metal, or carbon, nitrogen and metal, and forming an upper electrode on the phase-change material layer.Type: ApplicationFiled: February 8, 2012Publication date: June 7, 2012Inventors: Yong-Ho HA, Bong-Jin KUH, Han-Bong KO, Doo-Hwan PARK, Sang-Wook LIM, Hee-Ju SHIN
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Patent number: 8133429Abstract: In a method of forming a chalcogenide compound target, a first powder including germanium carbide or germanium is prepared, and a second powder including antimony carbide or antimony is prepared. A third powder including tellurium carbide or tellurium is prepared. A powder mixture is formed by mixing the first to the third powders. After a shaped is formed body by molding the powder mixture. The chalcogenide compound target is obtained by sintering the powder mixture. The chalcogenide compound target may include a chalcogenide compound that contains carbon and metal, or carbon, metal and nitrogen considering contents of carbon, metal and nitrogen, so that a phase-change material layer formed using the chalcogenide compound target may stable phase transition, enhanced crystallized temperature and increased resistance. A phase-change memory device including the phase-change material layer may have reduced set resistance and driving current while improving durability and sensing margin.Type: GrantFiled: April 19, 2010Date of Patent: March 13, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Ho Ha, Bong-Jin Kuh, Han-Bong Ko, Doo-Hwan Park, Sang-Wook Lim, Hee-Ju Shin
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Publication number: 20120032135Abstract: A phase-change material layer is formed on the lower electrode using a chalcogenide compound doped with carbon, or carbon and nitrogen. A phase-change material layer is obtained by doping a stabilizing metal into the preliminary phase-change material layer. An upper electrode is formed on the phase-change material layer. Since the phase-change material layer may have improved electrical characteristics, stability of phase transition and thermal stability, the phase-change memory unit may have reduced set resistance, enhanced durability, improved reliability, increased sensing margin, reduced driving current, etc.Type: ApplicationFiled: October 18, 2011Publication date: February 9, 2012Inventors: Bong-Jin KUH, Yong-Ho HA, Doo-Hwan PARK, Han-Bong KO, Sang-Wook LIM, Hee-Ju SHIN
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Publication number: 20110315946Abstract: A nonvolatile memory device, including a lower electrode on a semiconductor substrate, a phase change material pattern on the lower electrode, an adhesion pattern on the phase change material pattern and an upper electrode on the adhesion pattern, wherein the adhesion pattern includes a conductor including nitrogen.Type: ApplicationFiled: September 2, 2011Publication date: December 29, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Han-Bong KO, Yong-Ho Ha, Doo-Hwan Park, Bong-Jin Kuh, Hee-Ju Shin
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Patent number: 8026543Abstract: A phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation. In one embodiment, a semiconductor memory device includes a molding layer disposed over semiconductor substrate, a phase-changeable material pattern, and an oxidation barrier of electrically insulative material. The molding layer has a protrusion at its upper portion. One portion of the phase-changeable material pattern overlies the protrusion of the molding layer, and another portion of the phase-changeable material pattern extends through the protrusion. The electrically insulative material of the oxidation barrier may cover the phase-changeable material pattern and/or extend along and cover the entire area at which the protrusion of the molding layer and the portion of the phase-change material pattern disposed on the protrusion adjoin.Type: GrantFiled: December 18, 2008Date of Patent: September 27, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Yoon-Jong Song, Young-Nam Hwang, Sang-Don Nam, Sung-Lae Cho, Gwan-Hyeob Koh, Choong-Man Lee, Bong-Jin Kuh, Yong-Ho Ha, Su-Youn Lee, Chang-Wook Jeong, Ji-Hye Yi, Kyung-Chang Ryoo, Se-Ho Lee, Su-Jin Ahn, Soon-Oh Park, Jang-Eun Lee