Abstract: A thin film transistor array substrate having a high charge mobility and that can raise a threshold voltage, and a method of fabricating the thin film transistor array substrate are provided. The thin film transistor array substrate includes: an insulating substrate; a gate electrode formed on the insulating substrate; an oxide semiconductor layer comprising a lower oxide layer formed on the gate electrode and an upper oxide layer formed on the lower oxide layer, such that the oxygen concentration of the upper oxide layer is higher than the oxygen concentration of the lower oxide layer; and a source electrode and a drain electrode formed on the oxide semiconductor layer and separated from each other.

Abstract: The present invention relates to a method for forming a trench that can remove residual particles in a trench using a metal mask, a method for forming a metal wire, and a method for manufacturing a thin film transistor array panel. The method for forming a trench includes: forming a first insulating layer on a substrate; forming a first metal layer on the first insulating layer; forming an opening by patterning the first metal layer; forming a trench by dry-etching the first insulating layer using the patterned first metal layer as a mask; and wet-etching the substrate. The dry-etching is performed using a main etching gas and a first auxiliary etching gas, and the first auxiliary etching gas includes argon.

Abstract: A method of forming a metal pattern is provided. In the method, a first titanium layer, a copper layer and a second titanium layer are sequentially formed on a substrate. A photo pattern is formed on the second titanium layer. The first titanium layer, the copper layer and the second titanium layer are patterned using the photo pattern to form a first titanium pattern, a copper pattern formed on the first titanium pattern and a second titanium pattern formed on the copper pattern. Therefore, a fine metal pattern may be formed.

Abstract: Provided are a thin-film transistor (TFT) substrate, a method of manufacturing the same, and a display device including the same. The TFT substrate includes a gate electrode formed on a substrate, a gate insulating layer formed on the gate electrode, an oxide semiconductor pattern formed on the gate insulating layer, a source electrode formed on the oxide semiconductor pattern, a drain electrode formed on the oxide semiconductor pattern to face the source electrode, and a pixel electrode formed on the gate insulating layer.

Abstract: An etching composition for a copper-containing layer includes about 0.1% to about 30% by weight of ammonium persulfate, about 0.1% to about 10% by weight of a sulfate, about 0.01% to about 5% by weight of an acetate and about 55% to about 99.79% by weight of water.

Abstract: An etching composition and a method of manufacturing a display substrate using the etching composition are disclosed. The etching composition includes phosphoric acid (H3PO4) of about 40% by weight to about 70% by weight, nitric acid (HNO3) of about 5% by weight to about 15% by weight, acetic acid (CH3COOH) of about 5% by weight to about 20% by weight, and a remainder of water. Thus, a metal layer including copper may be stably etched.

Abstract: Provided is an etchant composition. The etchant composition according to an exemplary embodiment of the present invention includes ammonium persulfate ((NH4)2)S2O8, an azole-based compound, a water-soluble amine compound, a sulfonic acid-containing compound, a nitrate-containing compound, and water.

Abstract: Exemplary embodiments of the present invention provide a metal wiring etchant. A metal wiring etchant according to an exemplary embodiment of the present invention includes ammonium persulfate, an organic acid, an ammonium salt, a fluorine-containing compound, a glycol-based compound, and an azole-based compound.

Abstract: A composition for removing a photoresist, the composition including about 1% by weight to about 10% by weight of tetramethyl ammonium hydroxide (“TMAH”), about 1% by weight to about 10% by weight of an alkanol amine, about 50% by weight to about 70% by weight of a glycol ether compound, about 0.01% by weight to about 1% by weight of a triazole compound, about 20% by weight to about 40% by weight of a polar solvent, and water, each based on a total weight of the composition.

Abstract: An etchant includes about 0.1 percent by weight to about 30 percent by weight of ammonium persulfate (NH4)2S2O8, about 0.1 percent by weight to about 10 percent by weight of an inorganic acid, about 0.1 percent by weight to about 10 percent by weight of an acetate salt, about 0.01 percent by weight to about 5 percent by weight of a fluorine-containing compound, about 0.01 percent by weight to about 5 percent by weight of a sulfonic acid compound, about 0.01 percent by weight to about 2 percent by weight of an azole compound, and a remainder of water. Accordingly, the etchant may have high stability to maintain etching ability. Thus, manufacturing margins may be improved so that manufacturing costs may be reduced.

Abstract: A thin film transistor array substrate having a high charge mobility and that can raise a threshold voltage, and a method of fabricating the thin film transistor array substrate are provided. The thin film transistor array substrate includes: an insulating substrate; a gate electrode formed on the insulating substrate; an oxide semiconductor layer comprising a lower oxide layer formed on the gate electrode and an upper oxide layer formed on the lower oxide layer, such that the oxygen concentration of the upper oxide layer is higher than the oxygen concentration of the lower oxide layer; and a source electrode and a drain electrode formed on the oxide semiconductor layer and separated from each other.

Abstract: An etchant includes about 0.1 percent by weight to about 30 percent by weight of ammonium persulfate (NH4)2S2O8, about 0.1 percent by weight to about 10 percent by weight of an inorganic acid, about 0.1 percent by weight to about 10 percent by weight of an acetate salt, about 0.01 percent by weight to about 5 percent by weight of a fluorine-containing compound, about 0.01 percent by weight to about 5 percent by weight of a sulfonic acid compound, about 0.01 percent by weight to about 2 percent by weight of an azole compound, and a remainder of water. Accordingly, the etchant may have high stability to maintain etching ability. Thus, manufacturing margins may be improved so that manufacturing costs may be reduced.

Abstract: A thin film transistor array substrate having a high charge mobility and that can raise a threshold voltage, and a method of fabricating the thin film transistor array substrate are provided. The thin film transistor array substrate includes: an insulating substrate; a gate electrode formed on the insulating substrate; an oxide semiconductor layer comprising a lower oxide layer formed on the gate electrode and an upper oxide layer formed on the lower oxide layer, such that the oxygen concentration of the upper oxide layer is higher than the oxygen concentration of the lower oxide layer; and a source electrode and a drain electrode formed on the oxide semiconductor layer and separated from each other.

Abstract: An etchant includes about 0.1 percent by weight to about 30 percent by weight of ammonium persulfate (NH4)2S2O8, about 0.1 percent by weight to about 10 percent by weight of an inorganic acid, about 0.1 percent by weight to about 10 percent by weight of an acetate salt, about 0.01 percent by weight to about 5 percent by weight of a fluorine-containing compound, about 0.01 percent by weight to about 5 percent by weight of a sulfonic acid compound, about 0.01 percent by weight to about 2 percent by weight of an azole compound, and a remainder of water. Accordingly, the etchant may have high stability to maintain etching ability. Thus, manufacturing margins may be improved so that manufacturing costs may be reduced.

Abstract: A method for manufacturing a thin film transistor array panel, including: sequentially forming a first silicon layer, a second silicon layer, a lower metal layer, and an upper metal layer on a gate insulating layer and a gate line; forming a first film pattern on the upper metal layer; forming a first lower metal pattern and a first upper metal pattern that includes a protrusion, by etching the upper metal layer and the lower metal layer; forming first and second silicon patterns by etching the first and second silicon layers; forming a second film pattern by ashing the first film pattern; forming a second upper metal pattern by etching the first upper metal pattern; forming a data line and a thin film transistor by etching the first lower metal pattern and the first and second silicon patterns; and forming a passivation layer and a pixel electrode on the resultant.

Abstract: An etchant composition that allows simplification and optimization of semiconductor manufacturing process is presented, along with a method of patterning a conductive layer using the etchant and a method of manufacturing a flat panel display using the etchant. The etchant includes nitric acid, phosphoric acid, acetic acid, and an acetate compound in addition to water.

Abstract: A thin film transistor array and method of manufacturing the same include a pixel electrode formed of a transparent conductive layer on a substrate, a gate line formed of the transparent conductive layer and an opaque conductive layer on the substrate, a gate electrode connected to the gate line and formed of the transparent conductive layer and an opaque conductive layer on the substrate, a gate insulating layer which covers the gate line and the gate electrode, a semiconductor layer formed on the gate insulating layer to overlap the gate electrode, a data line which intersects the gate line, a source electrode connected to the data line to overlap a part of the semiconductor layer, and a drain electrode connected to the pixel electrode to overlap a part of the semiconductor layer.

Abstract: The present invention provides a stripping composition and a stripping method capable of easily stripping a color resist or an organic insulating film formed on a substrate to reuse the substrate when defects are found during a process of forming the color filter or organic insulating film on the substrate. In one embodiment, the stripping composition includes about 0.5 to about 45 wt % of hydroxide compound, about 10 to about 89 wt % of alkyleneglycolalkylether compound, about 5 to about 45 wt % of alkanolamine compound, and about 0.01 to about 5 wt % of inorganic salt compound. Advantageously, the stripping process can be performed without damaging a thin film transistor of a bottom substrate while removing the color resist or organic insulating film.

Abstract: A thin film transistor substrate and a method of manufacturing the thin film transistor substrate comprises forming a gate line and a data line intersecting each other with a gate insulating layer interposed and defining a pixel area on the substrate, a thin film transistor electrically connected to the gate line and the data line, and a stepped-structure occurring pattern overlapping at least one of the gate line and the data line; forming a passivation layer having a stepped-structure portion formed by the stepped-structure occurring pattern on the substrate; forming a photoresist pattern having a second stepped-structure portion corresponding to the stepped-structure portion on the passivation layer; patterning the passivation layer using the photoresist pattern as a mask; forming a transparent conductive layer on the substrate; and removing the photoresist pattern where the transparent conductive layer is covered by a stripper penetrating through the stepped-structure portion of the photoresist pattern an

Abstract: A method for manufacturing a TFT array panel includes forming a photosensitive film pattern with first and second parts in first and second sections on a metal layer, etching the metal layer of a third section using the film pattern as a mask to form first and second metal patterns, etching the film pattern to remove the first part, etching first and second amorphous silicon layers of the third section using the second part as a mask to form an amorphous silicon pattern and a semiconductor, etching the first and second metal patterns of the first section using the second part as a mask to form a source electrode and a drain electrode including an upper layer and a lower layer, and etching the amorphous silicon pattern of the region corresponding to the first section by using the second part as a mask to form an ohmic contact.