Abstract: A battery cell internal pressure measurement apparatus for measuring an internal pressure of at least one battery cell according to an example embodiment of the present disclosure may include a jig housing configured to accommodate the at least one battery cell, and a jig cover coupled to the jig housing and configured to cover the at least one battery cell. The at least one cell groove into which the at least one battery cell is inserted may be formed at a bottom of the jig housing.

Abstract: The present invention relates to a method and system for providing language learning services. The method of providing language learning services, according to the present invention, the method may include: activating, in response to receiving an input for acquiring a learning target image through a user terminal, a camera of the user terminal; specifying at least a portion of an image taken by the camera as the learning target image; receiving language learning information for the learning target image from a server; providing the language learning information to the user terminal; and storing, based on a request for storing of the language learning information, the language learning information in association with the learning target image, such that the learning target image is used in conjunction with learning of the language learning information.

Abstract: A system and method of designing an integrated circuit (IC) by considering a local layout effect are provided. The method of designing an IC may place instances of pre-placement cells so as to decrease occurrence of a local layout effect (LLE) causing structure. The method may extract a context of an instance from a peripheral layout of each of the placed instances to estimate an LLE of the instance, thereby analyzing a performance of the IC.

Abstract: An integrated circuit (IC) including a first synchronous circuit configured to operate in synchronization with a clock signal is provided. The first synchronous circuit includes a selector including a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, and a third input terminal configured to receive a scan enable signal indicating one of a scan test mode and a function operation mode and a latch unit configured to operate as a flip-flop outputting a first output signal corresponding to the first input signal in the scan test mode and to operate as a latch outputting a second output signal corresponding to the second input signal in the function operation mode.

Abstract: An integrated circuit (IC) including a first synchronous circuit configured to operate in synchronization with a clock signal is provided. The first synchronous circuit includes a selector including a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, and a third input terminal configured to receive a scan enable signal indicating one of a scan test mode and a function operation mode and a latch unit configured to operate as a flip-flop outputting a first output signal corresponding to the first input signal in the scan test mode and to operate as a latch outputting a second output signal corresponding to the second input signal in the function operation mode.

Abstract: A system and method of designing an integrated circuit (IC) by considering a local layout effect are provided. The method of designing an IC may place instances of pre-placement cells so as to decrease occurrence of a local layout effect (LLE) causing structure. The method may extract a context of an instance from a peripheral layout of each of the placed instances to estimate an LLE of the instance, thereby analyzing a performance of the IC.

Abstract: A method for managing network access is provided. The method includes determining whether there is a network connection request from at least one application, checking at least one attribute information item of the application, determining an access point name (APN) corresponding to the application based on the at least one attribute information item, and transmitting and receiving data of the application to/from a network using the determined APN.

Abstract: A method for managing network access is provided. The method includes determining whether there is a network connection request from at least one application, checking at least one attribute information item of the application, determining an access point name (APN) corresponding to the application based on the at least one attribute information item, and transmitting and receiving data of the application to/from a network using the determined APN.

Abstract: Example embodiments relate to a method performed by an apparatus for analyzing time of a semiconductor chip. The method may include defining a netlist, defining time delays of devices defined in the netlist, performing a normality test using the time delays, judging a p-value based on the normality test, and determining a time delay of the semiconductor chip.

Abstract: A mobile terminal includes a front body, a rear body, and a slide module connecting the front body to the rear body such that the front body is slidable with respect to the rear body, the slide module including a first slide member fixed to a front surface of the rear body and having a rail unit at both sides of the rear body, the rail unit having a specific length corresponding to a slide stroke of the front body; and a second slide member fixed to a rear surface of the front body and having a moving guide constrained to the rail unit at both sides of the rear body and slidably moved along the rail unit, in which the moving guide protrudes toward the rear body in order to receive the rail unit and cover the rail unit.

Abstract: Example embodiments relate to a method performed by an apparatus for analyzing time of a semiconductor chip. The method may include defining a netlist, defining time delays of devices defined in the netlist, performing a normality test using the time delays, judging a p-value based on the normality test, and determining a time delay of the semiconductor chip.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate; a dummy pattern extending in one direction on the semiconductor substrate; a junction region electrically connecting the dummy pattern to the semiconductor substrate; and a voltage applying unit that is configured to apply a bias voltage to the dummy pattern.

Abstract: In a method of estimating a leakage current in a semiconductor device, a chip including a plurality of cells is divided into segments by a grid model. Spatial correlation is determined as spatial correlation between process parameters concerned with the leakage currents in each of the cells. A virtual cell leakage characteristic function of a cell is generated by arithmetically operating actual leakage characteristic functions. A segment leakage characteristic function of a segment is generated by arithmetically operating the virtual cell leakage characteristic functions of all cells in the segment. Then, a full chip leakage characteristic function of the chip is generated by statistically operating the segment leakage characteristic functions of all segments in the chip. Accordingly, computational loads of Wilkinson's method for generating the full chip leakage characteristic function can remarkably be reduced.

Abstract: A circuit having an active clock shielding structure includes a logic circuit that receives a clock signal and performs a logic operation based on the clock signal, a power gating circuit that switches a mode of the logic circuit between an active mode and an sleep mode based on a power gating signal, a clock signal transmission line that transmits the clock signal to the logic circuit, and at least one power gating signal transmission line that transmits the power gating signal to the power gating circuit and functions as a shielding line pair with the clock signal transmission line.

Abstract: A power gating circuit includes a logic circuit, a switching element and a retention flip-flop. The logic circuit is coupled between a first power rail and a virtual power rail. The switching element selectively couples the virtual power rail to a second power rail in response to a mode control signal indicating an active mode or a standby mode. The retention flip-flop selectively performs a flip-flop operation or a data retention operation in response to a voltage of the virtual power rail.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate; a dummy pattern extending in one direction on the semiconductor substrate; a junction region electrically connecting the dummy pattern to the semiconductor substrate; and a voltage applying unit that is configured to apply a bias voltage to the dummy pattern.

Abstract: A mobile terminal includes a front body, a rear body, and a slide module connecting the front body to the rear body such that the front body is slidable with respect to the rear body, the slide module including a first slide member fixed to a front surface of the rear body and having a rail unit at both sides of the rear body, the rail unit having a specific length corresponding to a slide stroke of the front body; and a second slide member fixed to a rear surface of the front body and having a moving guide constrained to the rail unit at both sides of the rear body and slidably moved along the rail unit, in which the moving guide protrudes toward the rear body in order to receive the rail unit and cover the rail unit.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate; a dummy pattern extending in one direction on the semiconductor substrate; a junction region electrically connecting the dummy pattern to the semiconductor substrate; and a voltage applying unit that is configured to apply a bias voltage to the dummy pattern.

Abstract: A power gating circuit includes a logic circuit, a switching element and a retention flip-flop. The logic circuit is coupled between a first power rail and a virtual power rail. The switching element selectively couples the virtual power rail to a second power rail in response to a mode control signal indicating an active mode or a standby mode. The retention flip-flop selectively performs a flip-flop operation or a data retention operation in response to a voltage of the virtual power rail.

Abstract: In a method of estimating a leakage current in semiconductor device, a chip including a plurality of cells is divided into segments by a grid model. Spatial correlation is determined as spatial correlation between process parameters concerned with the leakage currents in each of the cells. A virtual cell leakage characteristic function of the cell is generated by arithmetically operating actual leakage characteristic functions. A segment leakage characteristic function is generated by arithmetically operating the virtual cell leakage characteristic functions of each cell in the segment. Then, a full chip leakage characteristic function is generated by statistically operating the segment leakage characteristic functions of each segment in the chip. Accordingly, the computational loads of Wilkinson's method for generating the full chip leakage characteristic function may be remarkably reduced.