Patents by Inventor Bonnie I. Wang
Bonnie I. Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8487665Abstract: Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.Type: GrantFiled: May 31, 2011Date of Patent: July 16, 2013Assignee: Altera CorporationInventors: Bonnie I. Wang, Chiakang Sung, Joseph Huang, Khai Nguyen, Philip Pan
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Patent number: 8384460Abstract: An adjustable delay circuit includes first and second transistors each having a control input coupled to an input node of the adjustable delay circuit and an output coupled to an output node of the adjustable delay circuit. The adjustable delay circuit includes a first pass gate coupled between first and second capacitors and the output node of the adjustable delay circuit. The first and the second capacitors are coupled between a node at a high voltage and a node at a low voltage. The first pass gate is operable to be controlled by a first delay control signal.Type: GrantFiled: March 14, 2012Date of Patent: February 26, 2013Assignee: Altera CorporationInventors: Chiakang Sung, John Henry Bui, Khai Nguyen, Bonnie I. Wang, Xiaobao Wang
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Publication number: 20120146700Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.Type: ApplicationFiled: December 13, 2011Publication date: June 14, 2012Applicant: ALTERA CORPORATIONInventors: Philip Pan, Chiakang Sung, Joseph Huang, Yan Chong, Bonnie I. Wang
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Publication number: 20120106264Abstract: Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.Type: ApplicationFiled: January 12, 2012Publication date: May 3, 2012Applicant: ALTERA CORPORATIONInventors: Yan Chong, Bonnie I. Wang, Chiakang Sung, Joseph Huang, Michael H.M. Chu
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Patent number: 8149038Abstract: A dynamic phase alignment circuit includes a phase generator circuit having delay-locked loop circuits that generate periodic output signals. Each of the delay-locked loop circuits generates one of the periodic output signals in response to at least two periodic input signals. A multiplexer circuit selects a selected periodic signal from among the periodic input signals and the periodic output signals based on select signals. A phase detection circuit compares a phase of the selected periodic signal to a data signal to generate a phase detection signal. A control logic circuit generates the select signals. The control logic circuit adjusts the select signals based on changes in the phase detection signal to cause the multiplexer circuit to adjust the phase of the selected periodic signal.Type: GrantFiled: March 22, 2010Date of Patent: April 3, 2012Assignee: Altera CorporationInventors: Chiakang Sung, John Henry Bui, Khai Nguyen, Bonnie I. Wang, Xiaobao Wang
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Patent number: 8122275Abstract: Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.Type: GrantFiled: August 22, 2007Date of Patent: February 21, 2012Assignee: Altera CorporationInventors: Yan Chong, Bonnie I. Wang, Chiakang Sung, Joseph Huang, Michael H. M. Chu
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Patent number: 8098082Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.Type: GrantFiled: November 24, 2010Date of Patent: January 17, 2012Assignee: Altera CorporationInventors: Philip Pan, Chiakang Sung, Joseph Huang, Yan Chong, Bonnie I. Wang
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Publication number: 20110227606Abstract: Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.Type: ApplicationFiled: May 31, 2011Publication date: September 22, 2011Applicant: ALTERA CORPORATIONInventors: Bonnie I. Wang, Chiakang Sung, Joseph Huang, Khai Nguyen, Philip Pan
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Patent number: 8022723Abstract: Circuits, methods, and apparatus for dynamic control of source and termination impedances. One output stage provides a series termination when transmitting and a parallel termination when receiving data. A pull-up device has a nominal impedance of 50 ohms when the output stage pulls a pin from a low voltage to a high voltage, while a pull-down device has a nominal impedance of 50 ohms when the pin is pulled from a high voltage to a low voltage. Both the pull-up and pull-down devices are turned on when receiving data. Due to their non-linear current-voltage characteristics, the pull-up device appears as 50 ohms when the pin voltage is higher than one half the supply voltage, while the pull-down device appears as 50 ohms when the pin voltage is lower than one half the supply voltage. The pull-up and pull-down devices can be calibrated to provide a nominal 50 ohm impedance.Type: GrantFiled: July 19, 2006Date of Patent: September 20, 2011Assignee: Altera CorporationInventors: Xiaobao Wang, Bonnie I. Wang, Chiakang Sung, Khai Q. Nguyen
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Patent number: 7973553Abstract: A circuit includes first transistors and a comparator. The comparator compares a reference signal and a signal that is based on conductive states of the first transistors. A control circuit generates first control signals based on an output signal of the comparator. The conductive states of the first transistors are determined based on the first control signals. An arithmetic circuit performs an arithmetic function based on the first control signals and second control signals to generate calibration signals. Second transistors provide a termination impedance at an external terminal of the circuit that is based on the calibration signals.Type: GrantFiled: March 11, 2010Date of Patent: July 5, 2011Assignee: Altera CorporationInventors: Xiaobao Wang, Chiakang Sung, Bonnie I. Wang, Khai Nguyen, John Henry Bui
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Patent number: 7859304Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.Type: GrantFiled: December 6, 2008Date of Patent: December 28, 2010Assignee: Altera CorporationInventors: Philip Pan, Chiakang Sung, Joseph Huang, Yan Chong, Bonnie I. Wang
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Patent number: 7725755Abstract: Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock signal and a first variable-delay block configured to receive an output from the frequency divider. Also included is a phase detector configured to receive the first clock signal and an output from the first variable-delay block, and an up/down counter configured to receive an output from the phase detector. A second variable-delay block is configured to receive a second clock signal and a plurality of flip-flops are configured to receive an output from the second variable-delay block. The first variable-delay block and the second variable-delay block are configured to receive an output from the up/down counter.Type: GrantFiled: January 29, 2007Date of Patent: May 25, 2010Assignee: Altera CorporationInventors: Yan Chong, Chiakang Sung, Bonnie I. Wang, Joseph Huang, Xiaobao Wang, Philip Pan, Tzung-Chin Chang
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Publication number: 20100045349Abstract: Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.Type: ApplicationFiled: August 11, 2009Publication date: February 25, 2010Applicant: Altera CorporationInventors: Bonnie I. Wang, Chiakang Sung, Joseph Huang, Khai Nguyen, Philip Pan
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Patent number: 7590879Abstract: Circuits, methods, and apparatus for deskewing rising and falling edges of a clock signal. One embodiment of the present invention utilizes a delay element in a data path to adjust a data signal such that a clock signal is centered relative to the data. A further embodiment of the present invention recovers a double-data rate signal using two flip-flops, one clocked by clock rising edges, the other clocked by clock falling edges. An additional delay element is inserted in front of one or both flip-flop clock inputs. If two additional delay elements are used, they are independently adjustable such that each edge can be independently adjusted for improved data recovery.Type: GrantFiled: January 24, 2005Date of Patent: September 15, 2009Assignee: Altera CorporationInventors: Henry Kim, Bonnie I. Wang, ChiaKang Sung, Joseph Huang
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Patent number: 7551014Abstract: Circuits and methods provide single-ended and differential signals. Single-ended drivers are used to, e.g., reduce pin capacitance. The output cell uses an inversion circuit, such as a phase splitter, to derive the differential signals from the same output signal and provide low skew between the differential signals at the output pins. Selection circuits are used to select between single-ended and differential output.Type: GrantFiled: February 1, 2007Date of Patent: June 23, 2009Assignee: Altera CorporationInventors: Bonnie I. Wang, Chiakang Sung, Khai Nguyen, Xiaobao Wang
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Patent number: 7477074Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.Type: GrantFiled: December 11, 2006Date of Patent: January 13, 2009Assignee: Altera CorporationInventors: Philip Pan, Chiakang Sung, Joseph Huang, Yan Chong, Bonnie I. Wang
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Publication number: 20080201597Abstract: Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.Type: ApplicationFiled: August 22, 2007Publication date: August 21, 2008Applicant: Altera CorporationInventors: Yan Chong, Bonnie I. Wang, Chiakang Sung, Joseph Huang, Michael H.M. Chu
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Publication number: 20080186056Abstract: Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.Type: ApplicationFiled: July 30, 2007Publication date: August 7, 2008Applicant: Altera CorporationInventors: Bonnie I. Wang, Chiakang Sung, Joseph Huang, Khai Nguyen, Philip Pan
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Patent number: 7358783Abstract: A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit. In an implementation, the programmable phase shift circuitry is implemented using two programmable counters.Type: GrantFiled: March 25, 2003Date of Patent: April 15, 2008Assignee: Altera CorporationInventors: Bonnie I. Wang, Joseph Huang, Chiakang Sung, Xiaobao Wang, In Whan Kim, Wayne Yeung, Khai Nguyen
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Patent number: 7324405Abstract: Circuits, methods, and apparatus for filtering signals at a high-speed data interface. One exemplary embodiment is particularly configured to filter a clock signal at the end of a data burst received by a double-data rate memory interface. A clock input port is either connected or disconnected to an input cell. When a data burst is to be received, the clock input port is connected to the input cell. When the data burst concludes, the clock input port is disconnected from the input cell. In a specific embodiment, a signal is received indicating that a data burst is about to begin and the clock input port is connected to the input cell. The signal later changes state indicating that the last data bit is being received. When the last clock edge corresponding to the last data bit is received, the clock input port is disconnected from the input cell.Type: GrantFiled: March 3, 2006Date of Patent: January 29, 2008Assignee: Altera CorporationInventors: Sanjay K. Charagulla, Chiakang Sung, Joseph Huang, Bonnie I. Wang, Yan Chong