Patents by Inventor Boon Teik CHAN

Boon Teik CHAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210035860
    Abstract: A method for forming a buried metal line in a substrate includes forming, at a position between a pair of semiconductor structures protruding from the substrate, a metal line trench in the substrate at a level below a base of each semiconductor structure of the pair. Forming the metal line trench includes etching an upper trench portion in the substrate, forming a spacer on sidewall surfaces of the upper trench portion that expose a bottom surface of the upper trench portion, and, while the spacer masks the sidewall surfaces, etching a lower trench portion by etching the substrate via the upper trench portion such that a width of the lower trench portion exceeds a width of the upper trench portion. The method further includes forming the metal line in the metal line trench.
    Type: Application
    Filed: August 1, 2020
    Publication date: February 4, 2021
    Inventors: Eugenio Dentoni Litta, Anshul Gupta, Julien Ryckaert, Boon Teik Chan
  • Publication number: 20210028059
    Abstract: A method for forming a buried metal line in a semiconductor substrate comprises forming, at a position between a pair of semiconductor structures, a metal line trench in the semiconductor substrate at a level below a base of each semiconductor structure of the pair, and forming the metal line in the metal line trench by means of area selective deposition of a metal line material, followed by embedding the pair of semiconductor structures in an insulating layer.
    Type: Application
    Filed: July 21, 2020
    Publication date: January 28, 2021
    Inventors: Boon Teik Chan, Zheng Tao, Efrain Altamirano Sanchez, Anshul Gupta, Basoene Briggs
  • Publication number: 20210020516
    Abstract: In one aspect, a method can include forming, by self-aligned multiple patterning, a first pattern of regularly spaced mandrels on a layer to be patterned; forming hard mask spacers on sidewalls of the mandrels, thereby forming a second pattern formed of assemblies comprising a mandrel and hard mask spacers on sidewalls thereof; and etching the second pattern in the layer to be patterned.
    Type: Application
    Filed: July 16, 2020
    Publication date: January 21, 2021
    Inventors: Boon Teik Chan, Yong Kong Siew, Juergen Boemmels
  • Patent number: 10825682
    Abstract: A method for producing a pillar structure in a semiconductor layer, the method including providing a structure including, on a main surface, a semiconductor layer. A patterned hard mask layer stack is provided on the semiconductor layer that includes a first layer in contact with the semiconductor layer and a second layer overlying and in contact with the first layer. The semiconductor layer is etched using the patterned hard mask layer stack as a mask. The etching includes subjecting the structure to a first plasma thereby removing a first part of the semiconductor layer and at least a part of the second layer while preserving the first layer thereby, producing a first part of the pillar structure, thereafter; and subjecting the structure to a second plasma thereby removing a second part of the semiconductor layer thereby, producing a second part of the pillar structure.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: November 3, 2020
    Assignee: IMEC VZW
    Inventors: Boon Teik Chan, Vasile Paraschiv, Efrain Altamirano Sanchez, Zheng Tao
  • Publication number: 20200328122
    Abstract: A method for forming a mask layer above a semiconductor fin structure is disclosed. In one aspect the method includes forming a first set of spacers and a second set of spacers arranged at the side surfaces of the first set of spacers, providing a first filler material between the second set of spacers, etching a top portion of the first filler material to form recesses between the second set of spacers, and providing a second filler material in the recesses, the second filler material forming a set of sacrificial mask lines. Further, the method includes recessing a top portion of at least the first set of spacers, providing a mask layer material between the sacrificial mask lines, and removing the sacrificial mask lines and the first filler material.
    Type: Application
    Filed: April 8, 2020
    Publication date: October 15, 2020
    Inventors: Boon Teik Chan, Zheng Tao, Efrain Altamirano Sanchez
  • Patent number: 10790382
    Abstract: A method for forming horizontal nanowires, the method comprising providing a substrate comprising a dielectric layer and a fin structure comprising a portion protruding from the dielectric layer, the protruding portion being partially un-masked and comprising a multi-layer stack consisting of a layer of a first material stacked alternately and repeatedly with a layer of a second material and forming horizontal nanowires done by performing a cycle comprising removing selectively the first material up to the moment that a horizontal nanowire of the second material becomes suspended over a remaining portion of the partially un-masked protruding portion, forming a sacrificial layer on the remaining portion, while leaving the suspended horizontal nanowire uncovered, providing, selectively, a cladding layer on the suspended horizontal nanowire, and thereafter removing the sacrificial layer.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: September 29, 2020
    Assignee: IMEC VZW
    Inventors: Boon Teik Chan, Silvia Armini, Elisabeth Camerotto, Zheng Tao
  • Patent number: 10784158
    Abstract: A method for forming a cavity in a semiconductor structure and an intermediate structure is provided. The method includes: (a) providing a semiconductor structure comprising: (i) a semiconductor substrate; (ii) a set of line structures on the semiconductor substrate, each line structure having a top surface and sidewalls, the line structures being separated by trenches therebetween, and (iii) an oxygen-containing dielectric material at least partially filling the trenches in-between the line structures, wherein the top surface of at least one of the line structures is at least partially exposed, and wherein the exposed part of the top surface is composed of an oxygen-free dielectric material; (b) forming a layer of TaSix selectively onto the oxygen-free dielectric material with respect to the oxygen-containing dielectric material (c) forming the cavity by selectively removing at least a portion of the oxygen-containing dielectric material with respect to the TaSix.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: September 22, 2020
    Assignee: IMEC VZW
    Inventors: Boon Teik Chan, Efrain Altamirano Sanchez
  • Patent number: 10782607
    Abstract: An example method for making a reticle includes providing an assembly. The assembly includes an extreme ultraviolet mirror and a cavity overlaying at least a bottom part of the extreme ultraviolet mirror. The method also includes at least partially filling the cavity with an extreme ultraviolet absorbing structure that includes a metallic material that includes an element selected from Ni, Co, Sb, Ag, In, and Sn, by forming the extreme ultraviolet absorbing structure selectively in the cavity.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: September 22, 2020
    Assignees: IMEC VZW, KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D
    Inventors: Boon Teik Chan, Kim Vu Luong, Vicky Philipsen, Efrain Altamirano Sanchez, Kevin Vandersmissen
  • Publication number: 20200168606
    Abstract: The disclosed technology relates to a method of forming a stacked semiconductor device. One aspect includes fin structures formed by upper and lower channel layers which are separated by an intermediate layer. After preliminary fun cuts are formed in the fin structure, a sacrificial spacer is formed that covers end surfaces of an upper channel layer portion. Final fin cuts are formed in the fin structure where the lower channel layer is etched which defines a lower channel layer portion. Lower source/drain regions are formed on end surfaces of the lower channel layer portion. The sacrificial spacer shields the end surfaces of the upper channel layer portion allowing for selective deposition of material for the lower source/drain regions.
    Type: Application
    Filed: November 26, 2019
    Publication date: May 28, 2020
    Inventors: Boon Teik Chan, Zheng Tao, Steven Demuynck
  • Publication number: 20200144094
    Abstract: In a first aspect, the present disclosure relates to a method for removing an organic sacrificial material from a 2D material, comprising: providing a target substrate having thereon the 2D material and a layer of the organic sacrificial material over the 2D material, infiltrating the organic sacrificial material with a metal or ceramic material, and removing the organic sacrificial material.
    Type: Application
    Filed: November 5, 2019
    Publication date: May 7, 2020
    Inventors: Boon Teik Chan, Jean-Francois de Marneffe, Daniil Marinov, Han Chung Lin, Inge Asselberghs
  • Publication number: 20200111892
    Abstract: According to an aspect of the disclosed technology, a method for forming a gate of a semiconductor device is disclosed. The method includes depositing a sacrificial material to form a preliminary sacrificial gate fill structure, etching back an upper surface of the preliminary sacrificial gate fill structure to obtain a final sacrificial gate fill structure, and replacing the sacrificial material of the final sacrificial gate fill structure with a conductive gate fill material by a conversion reaction, thereby forming a gate electrode of the semiconductor device. By replacing the sacrificial material with a conductive gate fill material rather than depositing and subsequently etching a conductive gate fill layer, surface of the conductive gate fill material is made relatively smooth.
    Type: Application
    Filed: October 9, 2019
    Publication date: April 9, 2020
    Inventors: Boon Teik Chan, Efrain Altamirano Sanchez, Annelies Delabie, Yoann Tomczak
  • Publication number: 20200083090
    Abstract: A substrate includes on its surface an array of dual stack semiconductor fins, each fin comprising a monocrystalline first portion, a polycrystalline second portion, and a mask third portion. Trenches between the fins are filled with shallow trench isolation (STI) oxide and with polycrystalline material, after which the surface is planarized. Then a second mask is produced on the planarized surface, the second mask defining at least one opening, each defined opening extending across an exposed fin. A thermal oxidation is performed of the polycrystalline material on either side of the exposed fin in each defined opening, thereby producing two oxide strips in each defined opening. Using the second mask and the oxide strips as a mask for self-aligned etching, the material of the exposed dual stack fins is removed and subsequently replaced by an electrically isolating material, thereby creating gate cut structures.
    Type: Application
    Filed: September 6, 2019
    Publication date: March 12, 2020
    Inventors: Boon Teik Chan, Efrain Altamirano Sanchez, Ryan Ryoung han Kim
  • Patent number: 10493378
    Abstract: A method for producing a structure including, on a main surface of a substrate, at least one elongated cavity having openings at opposing ends. The method includes providing a substrate having a main surface. On the main surface, a first pair of features are formed that protrude perpendicularly from the main surface. The features have elongated sidewalls and a top surface, are parallel to one another, are separated by a gap having a width s1 and a bottom area, and have a width w1 and a height h1. At least the main surface of the substrate and the first pair of features are brought in contact with a liquid, suitable for making a contact angle of less than 90° with the material of the elongated sidewalls and subsequently the substrate is dried.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: December 3, 2019
    Assignee: IMEC VZW
    Inventors: Zheng Tao, Boon Teik Chan, XiuMei Xu, Khashayar Babaei Gavan, Efrain Altamirano Sanchez
  • Patent number: 10490442
    Abstract: An example embodiment may include a method for blocking one or more portions of one or more trenches during manufacture of a semiconductor structure. The method may include (i) providing a substrate comprising one or more trenches, and a dielectric material under the one or more trenches, (ii) providing a first overlayer on the substrate, thereby filling the one or more trenches, the first overlayer having a planar top surface, a top portion of the first overlayer, comprising the top surface, being etchable selectively with respect to a condensed photo-condensable metal oxide, (iii) covering a first area of the top surface, situated directly above the one or more portions and corresponding thereto, with a block pattern of the condensed photo-condensable metal oxide, thereby leaving a second area of the top surface, having at least another portion of at least one of the trenches thereunder, uncovered.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: November 26, 2019
    Assignee: IMEC VZW
    Inventors: Boon Teik Chan, Ming Mao, Peter De Schepper, Michael Kocsis
  • Publication number: 20190355619
    Abstract: A method for forming a cavity in a semiconductor structure and an intermediate structure is provided. The method includes: (a) providing a semiconductor structure comprising: (i) a semiconductor substrate; (ii) a set of line structures on the semiconductor substrate, each line structure having a top surface and sidewalls, the line structures being separated by trenches therebetween, and (iii) an oxygen-containing dielectric material at least partially filling the trenches in-between the line structures, wherein the top surface of at least one of the line structures is at least partially exposed, and wherein the exposed part of the top surface is composed of an oxygen-free dielectric material; (b) forming a layer of TaSix selectively onto the oxygen-free dielectric material with respect to the oxygen-containing dielectric material (c) forming the cavity by selectively removing at least a portion of the oxygen-containing dielectric material with respect to the TaSix.
    Type: Application
    Filed: May 15, 2019
    Publication date: November 21, 2019
    Inventors: Boon Teik Chan, Efrain Altamirano Sanchez
  • Publication number: 20190271660
    Abstract: The disclosed technology generally relates to a method of forming a nanoscale opening in a semiconductor structure, and more particularly to forming a nanoscale opening that can be used for sensing the presence of polymers, e.g., the individual bases of deoxyribonucleic acid (DNA) or ribonucleic acid (RNA). In one aspect, a method of forming a nanopore in a semiconductor fin includes providing a fin structure comprising a bottom layer and a top layer, pattering the top layer to form a pillar, and laterally embedding the pillar in a filler material. The method additionally includes forming an aperture in the filler material by removing the pillar, and forming the nanopore in the bottom layer by etching through the aperture. In another aspect, a semiconductor fin is fabricated using the method.
    Type: Application
    Filed: March 4, 2019
    Publication date: September 5, 2019
    Inventors: Boon Teik Chan, Zheng Tao, Jean-Francois de Marneffe, Chang Chen
  • Publication number: 20190198643
    Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a vertical channel device and a method of fabricating the same. According to one aspect, a method for fabricating a vertical channel device includes forming a vertical semiconductor structure including an upper portion, an intermediate portion and a lower portion, by etching a semiconductor layer stack arranged on a substrate. The semiconductor layer stack includes an upper semiconductor layer, an intermediate semiconductor layer and a lower semiconductor layer, wherein the intermediate semiconductor layer is formed of a material different from a material of the lower semiconductor layer and different from a material of the upper semiconductor layer.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 27, 2019
    Inventors: Boon Teik Chan, Anabela Veloso, Efrain Altamirano Sanchez, Zheng Tao
  • Patent number: 10303048
    Abstract: The present disclosure relates to a patterned structure, the structure comprising: i) a substrate, ii) a first layer on top of the substrate, comprising a filler material and a guiding material, wherein at least a top surface of the first layer comprises one or more zones of filler material and one or more zones of guiding material, and iii) a second layer on top of the first layer comprising a pattern of a first material, the pattern being either aligned or anti-aligned with the underlying one or more zones of guiding material; wherein the first material comprises a metal or a ceramic material and wherein the guiding material and the filler material either both comprise or both do not comprise the metal or ceramic material.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: May 28, 2019
    Assignees: IMEC VZW, KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D
    Inventors: Boon Teik Chan, Arjun Singh, Safak Sayan
  • Publication number: 20190079384
    Abstract: An example method for making a reticle includes providing an assembly. The assembly includes an extreme ultraviolet mirror and a cavity overlaying at least a bottom part of the extreme ultraviolet mirror. The method also includes at least partially filling the cavity with an extreme ultraviolet absorbing structure that includes a metallic material that includes an element selected from Ni, Co, Sb, Ag, In, and Sn, by forming the extreme ultraviolet absorbing structure selectively in the cavity.
    Type: Application
    Filed: September 6, 2018
    Publication date: March 14, 2019
    Applicants: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&D
    Inventors: Boon Teik Chan, Kim Vu Luong, Vicky Philipsen, Efrain Altamirano Sanchez, Kevin Vandersmissen
  • Publication number: 20190057859
    Abstract: In one aspect, the present disclosure relates to a method. The method includes providing a substrate having a patterned layer thereon, the patterned layer including an opening that exposes the substrate. The method also includes selectively infiltrating the patterned layer with a metal or ceramic material, thereby reducing a dimension of the opening. The opening exposes the substrate after the dimension of the opening is reduced.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 21, 2019
    Applicant: IMEC VZW
    Inventors: Boon Teik Chan, Jean-Francois de Marneffe