Patents by Inventor Boon Teik CHAN

Boon Teik CHAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12154832
    Abstract: According to an aspect of the present inventive concept there is provided a method for forming source/drain contacts, the method comprising: depositing a material layer over a first and second layer stack formed in a first and second device region of a substrate, respectively, each layer stack comprising a number of semiconductor channel layers and the layer stacks being separated by a trench filled with insulating material to form an insulating wall between the layer stacks and between the device regions; forming a contact partition trench in the material layer at a position above the insulating wall, and filling the contact partition trench with an insulating material to form a contact partition wall on top of the insulating wall; forming a first and a second source/drain contact trench on mutually opposite sides of the contact partition wall, the first source/drain contact trench being formed above a source/drain region in the first device region, and the second source/drain contact trench being formed
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: November 26, 2024
    Assignee: IMEC VZW
    Inventors: Boon Teik Chan, Hans Mertens
  • Publication number: 20240373617
    Abstract: A three-dimensional (3D) static random access memory (SRAM) cell includes two PU transistors arranged in a first tier, two PD transistors arranged in a second tier positioned above or below the first tier, and two PG transistors arranged in the first or second tier. The transistors can be fin transistors, and each PU and PD transistor can have a first and second number of fins, respectively. The transistors can also be nanosheet-based transistors, and each PU and PD transistor can have a first and a second nanosheet width, respectively.
    Type: Application
    Filed: May 3, 2024
    Publication date: November 7, 2024
    Inventors: Hsiao-Hsuan Liu, Boon Teik Chan, Shairfe Muhammad Salahuddin
  • Publication number: 20240290660
    Abstract: Integrated circuit chips and method for making integrated circuit chips are provided. The method includes providing a semiconductor substrate, forming a device layer including a forksheet device on the substrate and providing the substrate with a substrate part of a dielectric wall of the forksheet device, a first shallow trench isolation and a second shallow trench isolation. The method also includes contacting a source or drain contact and extending into the substrate between the first shallow trench isolation and the dielectric wall, then removing the substrate material so as to expose an end of the dielectric wall, the first surface, and the second surface, then obtaining a first spacer and a second spacer, so as to obtain a trench, wherein the end of the dielectric wall is exposed to the trench, then depositing an electrically insulating material in the trench so as to form an extension.
    Type: Application
    Filed: December 5, 2023
    Publication date: August 29, 2024
    Inventors: Boon Teik Chan, Gaspard Hiblot, Gioele Mirabelli
  • Publication number: 20240234207
    Abstract: A method provided for interconnecting a buried wiring line and a source/drain body. The method includes: forming a fin structure on a substrate, the fin structure comprising at least one channel layer; forming a buried wiring line in a trench extending alongside the fin structure, wherein the buried wiring line is capped by a first insulating layer structure; forming a source/drain body on the at least one channel layer by epitaxy; forming a via hole in the first insulating layer structure to expose an upper surface of the buried wiring line; forming a metal via in the via hole; forming a second insulating layer structure over the first insulating layer structure, wherein a contact opening is defined in the second insulating layer structure to expose the source/drain body and an upper via portion of the metal via; and forming a source/drain contact in the contact opening, on the upper via portion and the source/drain body, thereby inter-connecting the buried wiring line and the source/drain body.
    Type: Application
    Filed: October 13, 2023
    Publication date: July 11, 2024
    Inventors: Boon Teik Chan, Hans Mertens, Zsolt Tokei, Naoto Horiguchi
  • Publication number: 20240213312
    Abstract: An integrated circuit device and method for forming the integrated circuit device are provided. The method includes: a) forming a semiconductor device on a frontside of a substrate comprising: a device layer on the frontside of the substrate, the device layer comprising a first active device, the substrate comprising: shallow trench isolation structures and a via filled with a sacrificial plug extending through the substrate material in a first separating portion; b) removing the substrate material from a backside of the substrate; c) depositing a liner covering the backside of the substrate; d) anisotropically etching the liner so as to expose a first end of the sacrificial plug, while retaining at least part of the liner in the separating portions; e) removing the sacrificial plug selectively with respect to the liner; and f) providing an electrically conductive material in the via, electrically coupled to a buried power rail.
    Type: Application
    Filed: November 20, 2023
    Publication date: June 27, 2024
    Inventors: Gaspard Hiblot, Boon Teik Chan, Gioele Mirabelli
  • Publication number: 20240204082
    Abstract: Example embodiments relate to methods for forming a semiconductor device. One example method includes forming a device structure on a substrate, where the device structure includes a device layer stack that includes a bottom device sub-stack that includes at least one bottom channel layer and a top device sub-stack that includes at least one top channel layer, a sacrificial gate structure extending across the device layer stack, and bottom source/drain structures on opposite ends of at least one bottom channel layer. The method also includes forming an opening exposing the top device sub-stack, wherein forming the opening includes etching the sacrificial gate structure, forming a cut through the top device sub-stack by etching back the top device sub-stack from the opening and, subsequent to forming the cut, forming a functional gate stack on the at least one bottom channel layer.
    Type: Application
    Filed: December 18, 2023
    Publication date: June 20, 2024
    Inventors: Boon Teik Chan, Shairfe Muhammad Salahuddin, Julien Ryckaert, Bilal Chehab, Hsiao-Hsuan Liu
  • Publication number: 20240206145
    Abstract: The present disclosure relates to static random access memory (SRAM). In particular, the disclosure provides a stacked SRAM cell, and a method for fabricating the stacked SRAM cell. The stacked SRAM cell comprises two first transistor structures and two second transistor structures, which form a pair of cross-coupled inverters, an comprises one or two pass gate (PG) transistor structures. Further, the stacked SRAM cell comprises a first power rail and/or a second power rail arranged above the transistor structures, wherein the first power rail is connected by respective first vias to the first transistor structures from above, and/or the second power rail is connected by respective second vias to the second transistor structures from above. The SRAM cell also comprises one or two bit lines arranged below the PG transistor structures. Each bit line is connected by a respective third via to one PG transistor structure from below.
    Type: Application
    Filed: December 19, 2023
    Publication date: June 20, 2024
    Inventors: Hsiao-Hsuan Liu, Shairfe Muhammad Salahuddin, Boon Teik Chan, Sujith Subramanian
  • Publication number: 20240204081
    Abstract: A method for forming a semiconductor device is disclosed. The method includes: forming a first bottom and top channel structures, and second bottom and top channel structures, and a sacrificial gate extending across the channel structures; forming an opening in the sacrificial gate, over the first top channel structure and forming a cut through the first top channel structure; forming a dielectric plug in the cut and the opening; removing the sacrificial gate and subsequently forming an RMG structure comprising a first gate stack on the first bottom channel structure and a second gate stack on the second bottom and top channel structures; forming pairs of S/D structures on the first bottom channel structure, the second bottom channel structure, and the second top channel structure; forming S/D contacts on the S/D structures; forming a trench for a cross-couple contact; and forming the cross-couple contact in the trench.
    Type: Application
    Filed: December 13, 2023
    Publication date: June 20, 2024
    Inventors: Boon Teik Chan, Hsiao-Hsuan Liu, Shairfe Muhammad Salahuddin
  • Publication number: 20240204080
    Abstract: A method for forming a semiconductor device is provided. The method includes: forming, over a substrate, a stacked transistor structure comprising: a bottom channel structure and a top channel structure, a gate structure extending across the bottom and top channel structures, a first and a second bottom S/D structure on the bottom channel structure, and a first and a second top S/D structure on the top channel structure; forming a first and a second bottom S/D contact on the first and the second bottom S/D structures; forming a contact isolation layer capping the first and second bottom S/D contacts, and covering the capped first and second bottom S/D contacts with an ILD layer; forming a first contact trench; forming a second contact trench; and forming a first top S/D contact.
    Type: Application
    Filed: December 13, 2023
    Publication date: June 20, 2024
    Inventors: Boon Teik Chan, Hsiao-Hsuan Liu, Pieter Schuddinck
  • Publication number: 20240154006
    Abstract: The disclosure relates to a method for forming a semiconductor device. The method includes: forming a device structure on a substrate, the device structure including a fin structure including a pair of source/drain bodies and a channel region between the pair of source/drain bodies, the channel region including at least one channel layer, and the device structure further including a gate structure extending across the channel region of the fin structure. The method also includes forming a metal layer over the source/drain bodies, etching the metal layer to define respective source/drain contacts on the source/drain bodies, and depositing an interlayer dielectric layer over the gate structure and the source/drain contacts.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 9, 2024
    Inventors: Zheng Tao, Boon Teik Chan
  • Publication number: 20240136225
    Abstract: A method provided for interconnecting a buried wiring line and a source/drain body. The method includes: forming a fin structure on a substrate, the fin structure comprising at least one channel layer; forming a buried wiring line in a trench extending alongside the fin structure, wherein the buried wiring line is capped by a first insulating layer structure; forming a source/drain body on the at least one channel layer by epitaxy; forming a via hole in the first insulating layer structure to expose an upper surface of the buried wiring line; forming a metal via in the via hole; forming a second insulating layer structure over the first insulating layer structure, wherein a contact opening is defined in the second insulating layer structure to expose the source/drain body and an upper via portion of the metal via; and forming a source/drain contact in the contact opening, on the upper via portion and the source/drain body, thereby inter-connecting the buried wiring line and the source/drain body.
    Type: Application
    Filed: October 12, 2023
    Publication date: April 25, 2024
    Inventors: Boon Teik Chan, Hans Mertens, Zsolt Tokei, Naoto Horiguchi
  • Publication number: 20240006228
    Abstract: A method for forming a buried metal line in a semiconductor substrate comprises forming, at a position between a pair of semiconductor structures, a metal line trench in the semiconductor substrate at a level below a base of each semiconductor structure of the pair, and forming the metal line in the metal line trench by means of area selective deposition of a metal line material, followed by embedding the pair of semiconductor structures in an insulating layer.
    Type: Application
    Filed: September 18, 2023
    Publication date: January 4, 2024
    Inventors: Boon Teik Chan, Zheng Tao, Efrain Altamirano Sanchez, Anshul Gupta, Basoene Briggs
  • Patent number: 11862452
    Abstract: In a first aspect, the present disclosure relates to a method for forming a contact isolation for a semiconductor device, comprising: providing a semiconductor structure comprising a trench exposing a contact thereunder, filling a bottom of the trench with a sacrificial material, infiltrating the sacrificial material with a ceramic material, and removing the sacrificial material.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: January 2, 2024
    Assignee: IMEC VZW
    Inventors: Boon Teik Chan, Waikin Li, Zheng Tao
  • Patent number: 11854803
    Abstract: A method for protecting a gate spacer when forming a FinFET structure, the method comprising: providing a fin with at least one dummy gate crossing the fin wherein a gate hardmask is present on top of the dummy gate; providing a gate spacer such that it is covering the dummy gate and the gate hardmask; recessing the gate spacer such that at least a part of the gate hardmask is exposed; selectively growing, by means of area selective deposition, extra capping material over the exposed part of the gate hardmask.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: December 26, 2023
    Assignee: IMEC VZW
    Inventors: Boon Teik Chan, Pierre Morin, Antony Premkumar Peter
  • Publication number: 20230413504
    Abstract: A bit cell for a Static Random-Access Memory (SRAM) is provided that includes first and second sets of transistors. Each set of transistors includes a respective pass-gate transistor and a respectively stacked complementary transistor pair of an upper transistor and a lower transistor. A source/drain terminal of a lower transistor of each set of transistors is connected to a respective first power supply extending in a first power supply track arranged below the lower transistor, whereas a source/drain terminal of an upper transistor of each set of transistors is connected to a respective second power supply extending in a second power supply track arranged above the upper transistor.
    Type: Application
    Filed: June 15, 2023
    Publication date: December 21, 2023
    Inventors: Hsiao-Hsuan Liu, Shairfe Muhammad Salahuddin, Boon Teik Chan
  • Publication number: 20230413505
    Abstract: A bit cell for a Static Random-Access Memory (SRAM) is provided that includes a first and second pair of complementary transistors as well as a first pass-gate transistor and a second pass-gate transistor. A first inverter gate electrode forms a common gate electrode for the first pair of complementary transistors and a second inverter gate electrode forms a common gate electrode for the second pair of complementary transistors. Further, a first pass gate electrode forms a gate of the first pass-gate transistor and a second pass gate electrode forms a gate of the second pass-gate transistor. A first and a second dielectric wall are also provided, separating the first pass gate electrode from the first inverter gate electrode, and the second pass gate electrode from the second inverter gate electrode.
    Type: Application
    Filed: June 15, 2023
    Publication date: December 21, 2023
    Inventors: Hsiao-Hsuan Liu, Shairfe Muhammad Salahuddin, Boon Teik Chan
  • Publication number: 20230386928
    Abstract: The present disclosure relates to a method for forming a stacked transistor device comprising a lower NSHFET structure and an upper FinFET structure including: forming a fin structure comprising: a lower device sub-stack comprising a number of lower channel nanosheets, a middle insulating layer, an upper device sub-stack comprising an upper channel layer, and a capping layer; forming a process layer embedding the fin structure; subsequent to forming the process layer, removing the capping layer from the fin structure to define a gap exposing the upper device sub-stack; forming spacer layers on opposite side surfaces of the gap to form a reduced-width gap; splitting the upper channel layer by etching back an upper surface thereof via the reduced-width gap to form two upper channel fins; subsequent to forming the upper channel fins, removing the spacer layers; and thereafter: forming a gate structure; and forming source and drain regions for the lower channel nanosheets and the upper channel fins.
    Type: Application
    Filed: May 23, 2023
    Publication date: November 30, 2023
    Inventors: Boon Teik Chan, Naoto Horiguchi, Julien Ryckaert
  • Patent number: 11824122
    Abstract: A method for partially filling a space between two superimposed structures in a semiconductor device under construction is provided. The method includes the steps of: (a) providing the two superimposed structures having said space therebetween; (b) entirely filling said space with a thermoplastic material; (c) removing a first portion of the thermoplastic material present in the space, the first portion comprising at least part of a top surface of the thermoplastic material, thereby leaving in said space a remaining thermoplastic material having a height; and (d) heating up the remaining photosensitive thermoplastic material so as to reduce its height. A replacement metal gate process for forming a different gate stack on two superimposed transistor channels in a semiconductor device under construction as well as a semiconductor device under construction is also provided.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: November 21, 2023
    Assignee: Imec vzw
    Inventors: Boon Teik Chan, Waikin Li, Zheng Tao
  • Publication number: 20230361205
    Abstract: A standard cell semiconductor device is provided that includes a first and second FET device, each including: (i) a source body and a drain body, each including a common source or drain body portion and a set of source or drain prongs protruding from the common source or drain body portion, (ii) a set of channel layers, each channel layer extending between a pair of source and drain prongs, and (iii) a gate body comprising a common gate body portion and a set of gate prongs protruding from the common gate body portion.
    Type: Application
    Filed: April 11, 2023
    Publication date: November 9, 2023
    Inventors: Boon Teik Chan, Bilal Chehab, Julien Ryckaert
  • Publication number: 20230197525
    Abstract: A method for forming a semiconductor device structure includes forming a layer stack comprising alternating sacrificial layers of a first semiconductor material and channel layers of a second semiconductor material. The method includes forming over the layer stack a plurality of parallel and regularly spaced core lines and forming spacer lines on side surfaces of the core lines. The method includes forming first trenches extending through the layer stack by etching the layer stack while using the core lines and the spacer lines as an etch mask and forming insulating walls in the first trenches and in the gaps by filling the first trenches and the gaps with insulating wall material. The method also includes forming second trenches extending through the layer stack by etching the layer stack while using the spacer lines and the insulating walls as an etch mask, thereby forming a plurality of pairs of fin structures.
    Type: Application
    Filed: December 19, 2022
    Publication date: June 22, 2023
    Inventors: Basoene Briggs, Boon Teik Chan, Juergen Boemmels