Patents by Inventor Bor Chiuan Hsieh

Bor Chiuan Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10672866
    Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Chun Huang, Bor Chiuan Hsieh, Pei-Ren Jeng, Tai-Chun Huang, Tze-Liang Lee
  • Publication number: 20200040450
    Abstract: Systems and methods for supplying a precursor material for an atomic layer deposition (ALD) process are provided. A gas supply provides one or more precursor materials to a deposition chamber. The deposition chamber receives the one or more precursor materials via an input line. A gas circulation system is coupled to an output line of the deposition chamber. The gas circulation system includes a gas composition detection system configured to produce an output signal indicating a composition of a gas exiting the deposition chamber through the output line. The gas circulation system also includes a circulation line configured to transport the gas exiting the deposition chamber to the input line. A controller is coupled to the gas supply. The controller controls the providing of the one or more precursor materials by the gas supply based on the output signal of the gas composition detection system.
    Type: Application
    Filed: October 14, 2019
    Publication date: February 6, 2020
    Inventors: Bor-Chiuan Hsieh, Chien-Kuo Huang, Tai-Chun Huang, Kuang-Yuan Hsu, Tze-Liang Lee
  • Patent number: 10510867
    Abstract: A method includes forming a dummy gate stack on a substrate, forming a spacer layer on the dummy gate stack, forming an etch stop layer over the spacer layer and the dummy gate stack, the etch stop layer comprising a vertical portion and a horizontal portion, and performing a densification process on the etch stop layer, wherein the horizontal portion is denser than the vertical portion after the densification process The method also includes forming an oxide layer over the etch stop layer, performing an anneal process on the oxide layer and the etch stop layer, wherein the vertical portion has a greater concentration of oxygen than the horizontal portion after the anneal process.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bor Chiuan Hsieh, Chung-Ting Ko, Ting-Gang Chen, Chien Chung Huang, Tai-Chun Huang, Tze-Liang Lee
  • Patent number: 10443127
    Abstract: Systems and methods for supplying a precursor material for an atomic layer deposition (ALD) process are provided. A gas supply provides one or more precursor materials to a deposition chamber. The deposition chamber receives the one or more precursor materials via an input line. A gas circulation system is coupled to an output line of the deposition chamber. The gas circulation system includes a gas composition detection system configured to produce an output signal indicating a composition of a gas exiting the deposition chamber through the output line. The gas circulation system also includes a circulation line configured to transport the gas exiting the deposition chamber to the input line. A controller is coupled to the gas supply. The controller controls the providing of the one or more precursor materials by the gas supply based on the output signal of the gas composition detection system.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: October 15, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Bor-Chiuan Hsieh, Chien-Kuo Huang, Tai-Chun Huang, Kuang-Yuan Hsu, Tze-Liang Lee
  • Publication number: 20190140076
    Abstract: A method includes forming a dummy gate stack on a substrate, forming a spacer layer on the dummy gate stack, forming an etch stop layer over the spacer layer and the dummy gate stack, the etch stop layer comprising a vertical portion and a horizontal portion, and performing a densification process on the etch stop layer, wherein the horizontal portion is denser than the vertical portion after the densification process The method also includes forming an oxide layer over the etch stop layer, performing an anneal process on the oxide layer and the etch stop layer, wherein the vertical portion has a greater concentration of oxygen than the horizontal portion after the anneal process.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 9, 2019
    Inventors: Bor Chiuan Hsieh, Chung-Ting Ko, Ting-Gang Chen, Chien Chung Huang, Tai-Chun Huang, Tze-Liang Lee
  • Patent number: 10157997
    Abstract: A method includes forming a dummy gate stack on a substrate, forming a spacer layer on the dummy gate stack, forming an etch stop layer over the spacer layer and the dummy gate stack, the etch stop layer comprising a vertical portion and a horizontal portion, and performing a densification process on the etch stop layer, wherein the horizontal portion is denser than the vertical portion after the densification process The method also includes forming an oxide layer over the etch stop layer, performing an anneal process on the oxide layer and the etch stop layer, wherein the vertical portion has a greater concentration of oxygen than the horizontal portion after the anneal process.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bor Chiuan Hsieh, Chung-Ting Ko, Ting-Gang Chen, Chien Chung Huang, Tai-Chun Huang, Tze-Liang Lee
  • Publication number: 20180350906
    Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.
    Type: Application
    Filed: July 24, 2018
    Publication date: December 6, 2018
    Inventors: Yen-Chun Huang, Bor Chiuan Hsieh, Pei-Ren Jeng, Tai-Chun Huang, Tze-Liang Lee
  • Publication number: 20180315830
    Abstract: A method includes forming a dummy gate stack on a substrate, forming a spacer layer on the dummy gate stack, forming an etch stop layer over the spacer layer and the dummy gate stack, the etch stop layer comprising a vertical portion and a horizontal portion, and performing a densification process on the etch stop layer, wherein the horizontal portion is denser than the vertical portion after the densification process The method also includes forming an oxide layer over the etch stop layer, performing an anneal process on the oxide layer and the etch stop layer, wherein the vertical portion has a greater concentration of oxygen than the horizontal portion after the anneal process.
    Type: Application
    Filed: August 2, 2017
    Publication date: November 1, 2018
    Inventors: Bor Chiuan Hsieh, Chung-Ting Ko, Ting-Gang Chen, Chien Chung Huang, Tai-Chun Huang, Tze-Liang Lee
  • Patent number: 10084040
    Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Chun Huang, Bor Chiuan Hsieh, Pei-Ren Jeng, Tai-Chun Huang, Tze-Liang Lee
  • Publication number: 20170194424
    Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.
    Type: Application
    Filed: October 11, 2016
    Publication date: July 6, 2017
    Inventors: Yen-Chun Huang, Bor Chiuan Hsieh, Pei-Ren Jeng, Tai-Chun Huang, Tze-Liang Lee
  • Patent number: 9437712
    Abstract: A method embodiment includes forming a protective liner over the substrate and forming an inter-layer dielectric over the protective liner. The protective liner covers a sidewall of a gate spacer. The method further includes patterning a contact opening in the first ILD to expose a portion of the protective liner. The portion of the protective liner in the contact opening is removed to expose an active region at a top surface of the semiconductor substrate. A contact is formed in the contact opening. The contact is electrically connected to the active region.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: September 6, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Chun Huang, Bor Chiuan Hsieh, Tai-Chun Huang, Chia-Ying Lee, Tze-Liang Lee
  • Patent number: 9218974
    Abstract: An integrated circuit structure includes a first gate strip; a gate spacer on a sidewall of the first gate strip; and a contact etch stop layer (CESL) having a bottom portion lower than a top surface of the gate spacer, wherein a portion of a sidewall of the gate spacer has no CESL formed thereon.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: December 22, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Hun-Jan Tao
  • Publication number: 20150255275
    Abstract: A method embodiment includes forming a protective liner over the substrate and forming an inter-layer dielectric over the protective liner. The protective liner covers a sidewall of a gate spacer. The method further includes patterning a contact opening in the first ILD to expose a portion of the protective liner. The portion of the protective liner in the contact opening is removed to expose an active region at a top surface of the semiconductor substrate. A contact is formed in the contact opening. The contact is electrically connected to the active region.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 10, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Chun Huang, Bor Chiuan Hsieh, Tai-Chun Huang, Chia-Ying Lee, Tze-Liang Lee
  • Publication number: 20150125591
    Abstract: Systems and methods for supplying a precursor material for an atomic layer deposition (ALD) process are provided. A gas supply provides one or more precursor materials to a deposition chamber. The deposition chamber receives the one or more precursor materials via an input line. A gas circulation system is coupled to an output line of the deposition chamber. The gas circulation system includes a gas composition detection system configured to produce an output signal indicating a composition of a gas exiting the deposition chamber through the output line. The gas circulation system also includes a circulation line configured to transport the gas exiting the deposition chamber to the input line. A controller is coupled to the gas supply. The controller controls the providing of the one or more precursor materials by the gas supply based on the output signal of the gas composition detection system.
    Type: Application
    Filed: November 5, 2013
    Publication date: May 7, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: BOR-CHIUAN HSIEH, CHIEN-KUO HUANG, TAI-CHUN HUANG, KUANG-YUAN HSU, TZE-LIANG LEE
  • Patent number: 8999834
    Abstract: An integrated circuit structure includes a first gate strip; a gate spacer on a sidewall of the first gate strip; and a contact etch stop layer (CESL) having a bottom portion lower than a top surface of the gate spacer, wherein a portion of a sidewall of the gate spacer has no CESL formed thereon.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Hun-Jan Tao
  • Patent number: 8900956
    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Ming-Jie Huang
  • Patent number: 8900957
    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Ming-Jie Huang
  • Publication number: 20140170846
    Abstract: An integrated circuit structure includes a first gate strip; a gate spacer on a sidewall of the first gate strip; and a contact etch stop layer (CESL) having a bottom portion lower than a top surface of the gate spacer, wherein a portion of a sidewall of the gate spacer has no CESL formed thereon.
    Type: Application
    Filed: February 20, 2014
    Publication date: June 19, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Hun-Jan Tao
  • Publication number: 20140073097
    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.
    Type: Application
    Filed: November 22, 2013
    Publication date: March 13, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Ming-Jie Huang
  • Publication number: 20140073096
    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.
    Type: Application
    Filed: November 22, 2013
    Publication date: March 13, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Ming-Jie Huang