Patents by Inventor Bor Chiuan Hsieh

Bor Chiuan Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140073096
    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.
    Type: Application
    Filed: November 22, 2013
    Publication date: March 13, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Ming-Jie Huang
  • Patent number: 8609497
    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: December 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Ming-Jie Huang
  • Publication number: 20130270651
    Abstract: An integrated circuit structure includes a first gate strip; a gate spacer on a sidewall of the first gate strip; and a contact etch stop layer (CESL) having a bottom portion lower than a top surface of the gate spacer, wherein a portion of a sidewall of the gate spacer has no CESL formed thereon.
    Type: Application
    Filed: June 7, 2013
    Publication date: October 17, 2013
    Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Hun-Jan Tao
  • Patent number: 8299508
    Abstract: A semiconductor device includes a substrate having shallow trench isolation and source/drain regions located therein, a gate stack located on the substrate between the source/drain regions, a first gate spacer on the sidewall of the gate stack, and a second gate spacer on the sidewall of the first gate spacer.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: October 30, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bor Chiuan Hsieh, Han-Ping Chung, Chih-Hsin Ko, Bor-Wen Chan, Hun-Jan Tao
  • Publication number: 20110201164
    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.
    Type: Application
    Filed: March 10, 2010
    Publication date: August 18, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Ming-Jie Huang
  • Patent number: 7947551
    Abstract: An embodiment of the disclosure includes a method of forming a shallow trench isolation structure. A substrate is provided. The substrate includes a top surface. A trench is formed to extend from the top surface into the substrate. The trench has sidewalls and a bottom surface. A silicon liner layer is formed on the sidewalls and the bottom surface. A flowable dielectric material is filled in the trench. An anneal process is performed to densify the flowable dielectric material and convert the silicon liner layer into a silicon oxide layer simultaneously.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: May 24, 2011
    Inventors: Sen-Hong Syue, Bor Chiuan Hsieh, Shiang-Bau Wang
  • Publication number: 20110084355
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an isolation feature disposed on the substrate, and an active area disposed adjacent the isolation feature. The isolation feature may be a shallow trench isolation feature. The STI feature has a first width at the top of the feature and a second width at the bottom of the feature. The first width is less than the second width. Methods of fabricating a semiconductor device is also provided. A method includes forming shallow trench isolation features and then growing an epitaxial layer adjacent the STI features to form an active region.
    Type: Application
    Filed: October 9, 2009
    Publication date: April 14, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Hsin Lin, Bor Chiuan Hsieh, Chen-Ping Chen
  • Publication number: 20110031538
    Abstract: A semiconductor device includes a substrate having shallow trench isolation and source/drain regions located therein, a gate stack located on the substrate between the source/drain regions, a first gate spacer on the sidewall of the gate stack, and a second gate spacer on the sidewall of the first gate spacer.
    Type: Application
    Filed: April 9, 2010
    Publication date: February 10, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bor Chiuan HSIEH, Han-Ping CHUNG, Chih-Hsin KO, Bor-Wen CHAN, Hun-Jan TAO
  • Publication number: 20100314690
    Abstract: An integrated circuit structure includes a first gate strip; a gate spacer on a sidewall of the first gate strip; and a contact etch stop layer (CESL) having a bottom portion lower than a top surface of the gate spacer, wherein a portion of a sidewall of the gate spacer has no CESL formed thereon.
    Type: Application
    Filed: March 30, 2010
    Publication date: December 16, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Hun-Jan Tao