Patents by Inventor Bor-Ping Jang

Bor-Ping Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8927391
    Abstract: A method of packaging includes placing a package component over a release film, wherein solder balls on a surface of the package component are in physical contact with the release film. Next, A molding compound filled between the release film and the package component is cured, wherein during the step of curing, the solder balls remain in physical contact with the release film.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Wei-Hung Lin, Sheng-Yu Wu, Chun-Cheng Lin, Kuei-Wei Huang, Yu-Peng Tsai, Chih-Wei Lin, Wen-Hsiung Lu, Hsiu-Jen Lin, Bor-Ping Jang, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 8884431
    Abstract: Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Lin, Ming-Da Cheng, Wen-Hsiung Lu, Hsiu-Jen Lin, Bor-Ping Jang, Chung-Shi Liu, Mirng-Ji Lii, Chen-Hua Yu, Meng-Tse Chen, Chun-Cheng Lin, Yu-Peng Tsai, Kuei-Wei Huang, Wei-Hung Lin
  • Publication number: 20140291881
    Abstract: A method includes placing a package structure into a mold chase, with top surfaces of device dies in the package structure contacting a release film in the mold chase. A molding compound is injected into an inner space of the mold chase through an injection port, with the injection port on a side of the mold chase. During the injection of the molding compound, a venting step is performed through a first venting port and a second venting port of the mold chase. The first venting port has a first flow rate, and the second port has a second flow rate different from the first flow rate.
    Type: Application
    Filed: June 12, 2014
    Publication date: October 2, 2014
    Inventors: Bor-Ping Jang, Yeong-Jyh Lin, Chien Ling Hwang, Chung-Shi Liu, Meng-Tse Chen, Ming-Da Cheng, Chen-Hua Yu
  • Publication number: 20140154871
    Abstract: A method for manufacturing a semiconductor device is provided. The method contains steps of providing the semiconductor device including a working area; directing a medium flow onto the working area; configuring a lens in contact with the medium flow; and directing a laser beam to the working area through the lens and the medium flow. A laser processing for manufacturing a semiconductor device is also provided.
    Type: Application
    Filed: November 30, 2012
    Publication date: June 5, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Ling Hwang, Bor-Ping Jang, Yi-Li Hsiao, Hsin-Hung Liao, Chung-Shi Liu
  • Patent number: 8702871
    Abstract: A method includes generating a solvent-containing vapor that contains a solvent. The solvent-containing vapor is conducted to a package assembly to clean the package assembly. The solvent-containing vapor condenses to form a liquid on a surface of the package assembly, and flows off from the surface of the package assembly.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Li Hsiao, Bor-Ping Jang, Kuei-Wei Huang, Lin-Wei Wang, Chien Ling Hwang, Chung-Shi Liu
  • Publication number: 20140048586
    Abstract: The present disclosure is directed to an apparatus for the application of soldering flux to a semiconductor workpiece. In some embodiments the apparatus comprises a dipping plate having a reservoir which is adapted to containing different depths of flux material. In some embodiments, the reservoir comprises at least two landing regions having sidewalls which form first and second dipping zones. The disclosed apparatus can allow dipping of the semiconductor workpiece in different depths of soldering flux without the necessity for changing dipping plates.
    Type: Application
    Filed: August 15, 2012
    Publication date: February 20, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bor-Ping Jang, Lin-Wei Wang, Ying-Jui Huang, Yi-Li Hsiao, Chien Ling Hwang, Chung-Shi Liu
  • Patent number: 8616433
    Abstract: A method of forming a bump structure includes providing a first work piece including a dielectric layer having a top surface; placing a second work piece facing the first work piece; placing a heating tool contacting the second work piece; and heating the second work piece using the heating tool to perform a reflow process. A first solder bump between the first and the second work pieces is melted to form a second solder bump. Before the second solder bump solidifies, pulling the second work piece away from the first work piece, until an angle formed between a tangent line of the second solder bump and the top surface of the dielectric layer is greater than about 50 degrees, wherein the tangent line is drawn at a point where the second solder bump joins the dielectric layer.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: December 31, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Wei Huang, Wei-Hung Lin, Lin-Wei Wang, Bor-Ping Jang, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20130273717
    Abstract: The present disclosure is directed to an apparatus for the singulation of a semiconductor substrate or wafer. In some embodiments the singulation apparatus comprises a plurality of cutting devices. The cutting devices are configured to form multiple concurrent cutting lines in parallel on a surface of the semiconductor wafer. In some embodiments, the singulation apparatus comprises at least two dicing saws or laser modules. The disclosed singulation apparatus can dice the semiconductor wafer into individual chips by dicing in a direction across a complete circumferential edge of the wafer, thereby decreasing process time and increasing throughput.
    Type: Application
    Filed: April 17, 2012
    Publication date: October 17, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien Ling Hwang, Yi-Li Hsiao, Bor-Ping Jang, Hsin-Hung Liao, Lin-Wei Wang, Chung-Shi Liu
  • Patent number: 8556158
    Abstract: A method includes providing a substrate carrier including work piece holders, and placing a first plurality of work pieces into the work piece holders. A second plurality of work pieces is picked up and placed, with each of the second plurality of work pieces being placed on one of the first plurality of work pieces. Solder bumps between the first and the second plurality of work pieces are then reflowed to simultaneously bond the first and the second plurality of work pieces together.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: October 15, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bor-Ping Jang, Kuei-Wei Huang, Wei-Hung Lin, Chung-Shi Liu
  • Publication number: 20130228951
    Abstract: A mold includes a top portion, and an edge ring having a ring-shape. The edge ring is underlying and connected to edges of the top portion. The edge ring includes air vents. The edge ring further encircles the inner space under the top portion of the mold. A plurality of injection ports is connected to the inner space of the mold. The plurality of injection ports is substantially aligned to a straight line crossing a center of the top portion of the mold. The plurality of injection ports has different sizes.
    Type: Application
    Filed: March 2, 2012
    Publication date: September 5, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bor-Ping Jang, Yeong-Jyh Lin, Chien Ling Hwang, Chung-Shi Liu
  • Publication number: 20130146647
    Abstract: A method includes reflowing a solder region of a package structure, and performing a cleaning on the package structure at a cleaning temperature higher than a room temperature. Between the step of reflowing and the step of cleaning, the package structure is not cooled to temperatures close to the room temperature.
    Type: Application
    Filed: December 7, 2011
    Publication date: June 13, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Shi Liu, Chien Ling Hwang, Bor-Ping Jang, Ying-Jui Huang
  • Publication number: 20130062761
    Abstract: Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL.
    Type: Application
    Filed: September 9, 2011
    Publication date: March 14, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Lin, Ming-Da Cheng, Wen-Hsiung Lu, Hsiu-Jen Lin, Bor-Ping Jang, Chung-Shi Liu, Mirng-Ji Lii, Chen-Hua Yu, Meng-Tse Chen, Chun-Cheng Lin, Yu-Peng Tsai, Kuei-Wei Huang, Wei-Hung Lin
  • Publication number: 20130048027
    Abstract: A method includes generating a solvent-containing vapor that contains a solvent. The solvent-containing vapor is conducted to a package assembly to clean the package assembly. The solvent-containing vapor condenses to form a liquid on a surface of the package assembly, and flows off from the surface of the package assembly.
    Type: Application
    Filed: August 30, 2011
    Publication date: February 28, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Li Hsiao, Bor-Ping Jang, Kuei-Wei Huang, Lin-Wei Wang, Chien Ling Hwang, Chung-Shi Liu
  • Patent number: 8381965
    Abstract: A method includes providing a substrate carrier including work piece holders, and placing a first plurality of work pieces into the work piece holders. A second plurality of work pieces is picked up and placed, with each of the second plurality of work pieces being placed on one of the first plurality of work pieces. Solder bumps between the first and the second plurality of work pieces are then reflowed to simultaneously bond the first and the second plurality of work pieces together.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: February 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bor-Ping Jang, Kuei-Wei Huang, Wei-Hung Lin, Chung-Shi Liu
  • Patent number: 8360303
    Abstract: A method of forming a bump structure includes providing a first work piece including a dielectric layer having a top surface; placing a second work piece facing the first work piece; placing a heating tool contacting the second work piece; and heating the second work piece using the heating tool to perform a reflow process. A first solder bump between the first and the second work pieces is melted to form a second solder bump. Before the second solder bump solidifies, pulling the second work piece away from the first work piece, until an angle formed between a tangent line of the second solder bump and the top surface of the dielectric layer is greater than about 50 degrees, wherein the tangent line is drawn at a point where the second solder bump joins the dielectric layer.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: January 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Wei Huang, Wei-Hung Lin, Lin-Wei Wang, Bor-Ping Jang, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20120299181
    Abstract: A method of packaging includes placing a package component over a release film, wherein solder balls on a surface of the package component are in physical contact with the release film. Next, A molding compound filled between the release film and the package component is cured, wherein during the step of curing, the solder balls remain in physical contact with the release film.
    Type: Application
    Filed: May 27, 2011
    Publication date: November 29, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Wei-Hung Lin, Sheng-Yu Wu, Chun-Cheng Lin, Kuei-Wei Huang, Yu-Peng Tsai, Chih-Wei Lin, Wen-Hsiung Lu, Hsiu-Jen Lin, Bor-Ping Jang, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20120267423
    Abstract: A vacuum tip and methods for processing thin integrated circuit dies. A vacuum tip for attaching to an integrated circuit die is disclosed comprising a vacuum port configured to connect to a vacuum supply on an upper surface and having a bottom surface; and at least one vacuum hole extending through the vacuum tip and exposed at the bottom surface of the vacuum tip; wherein the vacuum tip is configured to physically contact a surface of an integrated circuit die. Methods for processing integrated circuit dies are disclosed.
    Type: Application
    Filed: April 19, 2011
    Publication date: October 25, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Wei Huang, Wei-Hung Lin, Meng-Tse Chen, Chun-Cheng Lin, Yu-Peng Tsai, Bor-Ping Jang, Chung-Shi Liu
  • Publication number: 20120018494
    Abstract: A method includes providing a substrate carrier including work piece holders, and placing a first plurality of work pieces into the work piece holders. A second plurality of work pieces is picked up and placed, with each of the second plurality of work pieces being placed on one of the first plurality of work pieces. Solder bumps between the first and the second plurality of work pieces are then reflowed to simultaneously bond the first and the second plurality of work pieces together.
    Type: Application
    Filed: July 22, 2010
    Publication date: January 26, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bor-Ping Jang, Kuei-Wei Huang, Wei-Hung Lin, Chung-Shi Liu
  • Publication number: 20120021183
    Abstract: A method of forming a bump structure includes providing a first work piece including a dielectric layer having a top surface; placing a second work piece facing the first work piece; placing a heating tool contacting the second work piece; and heating the second work piece using the heating tool to perform a reflow process. A first solder bump between the first and the second work pieces is melted to form a second solder bump. Before the second solder bump solidifies, pulling the second work piece away from the first work piece, until an angle formed between a tangent line of the second solder bump and the top surface of the dielectric layer is greater than about 50 degrees, wherein the tangent line is drawn at a point where the second solder bump joins the dielectric layer.
    Type: Application
    Filed: July 22, 2010
    Publication date: January 26, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Wei Huang, Wei-Hung Lin, Lin-Wei Wang, Bor-Ping Jang, Ming-Da Cheng, Chung-shi Liu
  • Patent number: 7005236
    Abstract: Maintaining photoresist thickness and uniformity over a substrate that includes various cavities presents problems, such as preventing distortion of features in the resist image close to cavity edges. These problems have been overcome by laying down the photoresist as two separate layers. The first layer is used to eliminate or reduce problems associated with the presence of the cavities. The second layer is processed in the normal way and does not introduce distortions close to a cavity's edge. A first embodiment introduces some liquid into the cavity before laying down the first layer while the second embodiment etches away part of the first layer before applying the second one. Application of the process to the formation of a cantilever that overhangs a cavity is also described.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: February 28, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Su-Jen Cheng, Bor-Ping Jang, Chun-Chieh Wang, Jy-Jie Gau