Patents by Inventor Bor-Wen Chan
Bor-Wen Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6828237Abstract: A plasma etch method for forming a patterned target layer within a microelectrcnic product forms an etch residue layer adjoining a patterned mask layer formed upon a blanket target layer. After removing the patterned mask layer, the etch residue layer is laterally increased to form a laterally increased etch residue layer. The laterally increased etch residue layer is employed as an etch mask for forming the patterned target layer from the blanket target layer. The method is particularly useful for forming gate electrodes within semiconductor products.Type: GrantFiled: September 11, 2003Date of Patent: December 7, 2004Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Bor-Wen Chan, Fang-Cheng Chen, Hsien-Kuang Chiu, Yuan-Hung Chiu, Han-Jan Tao
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Patent number: 6812044Abstract: A method for monitoring plasma parameters during a plasma process such as a plasma etching process, comparing the measured plasma parameters to predetermined parameter specifications, and either terminating the plasma process or modifying the plasma process in progress to re-establish the plasma parameters within the parameter specifications. The plasma parameters may be measured by the self-excited electron resonance spectroscopy (SEEKS) technique or by microwave interferometry.Type: GrantFiled: December 19, 2002Date of Patent: November 2, 2004Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Hsien-Kuang Chiu, Bor-Wen Chan, Baw-Ching Perng, Yuan-Hung Chiu, Hun-Jan Tao
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Publication number: 20040214448Abstract: A method is provided for stripping a photoresist with a carbonized crust formed during a high dose ion implant. The method may be performed in any etch tool or asher including those where a plasma is generated with a RF discharge source and bias power and tools with a microwave downstream plasma flow. An ICP plasma source is preferred for generating plasma from a flow of oxygen and one or more CxHyFz gases such as CH3F and CH2F2 where x, y and z are ≧1. A high photoresist removal rate of from 0.2 to 2 microns per minute is achieved while reducing thickness loss in exposed oxide, polysilicon, and silicon layers compared with conventional methods that employ O2 and CMFN gases. For NMOS and PMOS transistors, Idsat and contact junction leakage are improved.Type: ApplicationFiled: April 22, 2003Publication date: October 28, 2004Applicant: Taiwan Semiconductor Manufacturing Co.Inventors: Bor-Wen Chan, Yuan-Hung Chiu, Han-Jan Tao
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Publication number: 20040142531Abstract: A process for forming a DRAM stacked capacitor structure with increased surface area, has been developed. The process features forming lateral grooves in the sides of a polysilicon storage node structure, during a dry etching procedure used to define the storage node structure. The grooves are selectively, and laterally formed in ion implanted veins, which in turn had been placed at various depths in an intrinsic polysilicon layer via a series of ion implantation steps, each performed at a specific implant energy. An isotopic component of the storage node structure, defining dry etch procedure, selectively etches the highly doped, ion implanted veins at a greater rate than the non-ion implanted regions of polysificon, located between the ion implanted veins, resulting in a necked profile, storage node structure, featuring increased surface area as a result of the formation of the lateral grooves.Type: ApplicationFiled: January 12, 2004Publication date: July 22, 2004Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Bor-Wen Chan, Huan-Just Lin, Hun-Jan Tao
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Patent number: 6764903Abstract: A method for forming a patterned target layer from a blanket target layer employs a pair of blanket hard mask layers laminated upon the blanket target layer. A patterned third mask layer is formed thereover. The method also employs four separate etch steps. One etch step is an anisotropic etch step for forming a patterned upper lying hard mask layer from the blanket upper lying hard mask layer. The patterned upper lying hard mask layer is then isotropically etched in a second etch step to form an isotropically etched patterned upper lying hard mask layer. The method is particularly useful for forming gate electrodes of diminished linewidths and enhanced dimensional control within semiconductor products.Type: GrantFiled: April 30, 2003Date of Patent: July 20, 2004Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Bor-Wen Chan, Yuan-Hung Chiu, Hun-Jan Tao
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Publication number: 20040121603Abstract: A method for monitoring plasma parameters during a plasma process such as a plasma etching process, comparing the measured plasma parameters to predetermined parameter specifications, and either terminating the plasma process or modifying the plasma process in progress to re-establish the plasma parameters within the parameter specifications. The plasma parameters may be measured by the self-excited electron resonance spectroscopy (SEEKS) technique or by microwave interferometry.Type: ApplicationFiled: December 19, 2002Publication date: June 24, 2004Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsien-Kuang Chiu, Bor-Wen Chan, Baw-Ching Perng, Yuan-Hung Chiu, Hun-Jan Tao
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Patent number: 6713398Abstract: A method of planarizing a polysilicon plug. A dielectric layer has an opening therein. Polysilicon is deposited into the opening to form a polysilicon layer so that the opening is completely filled and the top surface of the dielectric layer is covered. A high molecular weight compound is deposited to form a sacrificial film over the polysilicon layer. An anisotropic etching of the sacrificial film and the polysilicon layer is carried out to remove the sacrificial film and the polysilicon layer outside the opening.Type: GrantFiled: November 16, 1999Date of Patent: March 30, 2004Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Bor-Wen Chan
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Patent number: 6706591Abstract: A process for forming a DRAM stacked capacitor structure with increased surface area, has been developed. The process features forming lateral grooves in the sides of a polysilicon storage node structure, during a dry etching procedure used to define the storage node structure. The grooves are selectively, and laterally formed in ion implanted veins, which in turn had been placed at various depths in an intrinsic polysilicon layer via a series of ion implantation steps, each performed at a specific implant energy. An isotopic component of the storage node structure, defining dry etch procedure, selectively etches the highly doped, ion implanted veins at a greater rate than the non-ion implanted regions of polysilicon, located between the ion implanted veins, resulting in a necked profile, storage node structure, featuring increase surface area as a result of the formation of the lateral grooves.Type: GrantFiled: January 22, 2002Date of Patent: March 16, 2004Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Bor-Wen Chan, Huan-Just Lin, Hun-Jan Tao
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Patent number: 6656796Abstract: Within a method for fabricating a split gate field effect transistor (FET) device there is employed a two step etch method for forming a floating gate electrode. Within the two step etch method there is employed a patterned first masking layer and a blanket second masking layer to assist in providing the floating gate electrode with a sharply pointed tip within at least either an upper edge of the floating gate electrode or sidewall of the floating gate electrode. The sharply pointed tip provides the split gate field effect transistor (FET) device with enhanced data erasure performance.Type: GrantFiled: January 14, 2002Date of Patent: December 2, 2003Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Bor-Wen Chan, Yu-I Wang, Chen-Yuan Hsu, Hun-Jan Tao
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Publication number: 20030134435Abstract: Within a method for fabricating a split gate field effect transistor (FET) device there is employed a two step etch method for forming a floating gate electrode. Within the two step etch method there is employed a patterned first masking layer and a blanket second masking layer to assist in providing the floating gate electrode with a sharply pointed tip within at least either an upper edge of the floating gate electrode or sidewall of the floating gate electrode. The sharply pointed tip provides the split gate field effect transistor (FET) device with enhanced data erasure performance.Type: ApplicationFiled: January 14, 2002Publication date: July 17, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bor-Wen Chan, Yu-I Wang, Chen-Yuan Hsu, Hun-Jan Tao
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Patent number: 6503848Abstract: A method is disclosed for smoothing the top surface of a layer of polysilicon which, as deposited, has a rough top surface due to the formation of polysilicon grains. A polymer, such as CxFyBrz, is deposited using chemical vapor deposition. The polymer layer has a thickness large enough so that the top surface of the polymer is at least a critical distance above the peaks of the grains on the top surface of the layer of polysilicon. The layer of polymer and part of the layer of polysilicon are then etched away using an etch back method which etches the polymer and polysilicon at the same etch rate. This results in a layer of polysilicon having a smooth top surface and the same thickness over the entire layer of polysilicon.Type: GrantFiled: November 20, 2001Date of Patent: January 7, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Bor-Wen Chan, Yuan-Hung Chiu, Huan-Just Lin, Hun-Jan Tao
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Patent number: 6440875Abstract: Within a method for forming a spacer layer, there is first provided a substrate having formed thereover a topographic feature in turn having formed thereover a second microelectronic layer formed of a second material having a second thickness in turn having formed thereover a first microelectronic layer formed of a first material having a first thickness. Within the method, the first material serves as an etch stop for second material and the first thickness is less than the second thickness. The first microelectronic layer and the second microelectronic layer are then successively etched to ultimately form a spacer layer with enhanced dimensional control.Type: GrantFiled: May 2, 2001Date of Patent: August 27, 2002Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Bor-Wen Chan, Mei-Ru Kuo
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Publication number: 20020068460Abstract: A method of planarizing a polysilicon plug. A dielectric layer has an opening therein. Polysilicon is deposited into the opening to form a polysilicon layer so that the opening is completely filled and the top surface of the dielectric layer is covered. A high molecular weight compound is deposited to form a sacrificial film over the polysilicon layer. An anisotropic etching of the sacrificial film and the polysilicon layer is carried out to remove the sacrificial film and the polysilicon layer outside the opening.Type: ApplicationFiled: November 16, 1999Publication date: June 6, 2002Inventor: BOR-WEN CHAN
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Patent number: 6399286Abstract: A fabrication method for reducing the critical dimension of the conductive line and the space is described in which a conductive layer and a mask layer are sequentially formed on a substrate. A taper etching is conducted to form a plurality of first openings with the cross-sections of the openings being tapered off from top to bottom and exposing the surface of the conductive layer. A planarized sacrificial layer at a similar height as the mask layer is formed covering the exposed surface of the conductive layer. A second taper etching is further conducted on the exposed mask layer to form a plurality of second openings with the cross-sections of the openings being tapered off from top to bottom. The sacrificial layer is then removed. Thereafter, an anisotropic etching is conducted on the exposed conductive layer, using the mask layer as a hard mask, to form a plurality of conductive lines followed by a removal of the mask layer.Type: GrantFiled: August 26, 1999Date of Patent: June 4, 2002Assignee: Taiwan Semiconductor Manufacturing Corp.Inventors: Yuan-Hung Liu, Bor-Wen Chan
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Patent number: 6352919Abstract: A method of fabricating a borderless via is disclosed. A semiconductor substrate having a first dielectric layer thereon is provided. Next, a first conductive structure and a second conductive structure whose area is much smaller than said first conductive structure are formed on said first dielectric layer. After that, a second dielectric layer with an uneven surface is formed. Then, a planarizing layer is coated over said second dielectric layer to fill said uneven surface. Next, an etch back process is used to create a etching stop layer consisting of a portion of second dielectric layer. Subsequently, a third dielectric layer is formed over said second dielectric layer followed by selectively etching said third dielectric layer until said second dielectric layer is exposed to create a borderless via.Type: GrantFiled: July 20, 2000Date of Patent: March 5, 2002Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yeur-Luen Tu, Bor-Wen Chan, Yuan-Hung Liu
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Patent number: 6291312Abstract: A method for forming a pullback opening above a shallow trench isolation structure. A patterned mask layer is formed over a substrate. A sacrificial layer is formed on the sidewalls of the mask layer. The exposed portion of the substrate is etched to form a trench in the substrate. The sacrificial layer is removed to increase the width of the opening above the trench.Type: GrantFiled: September 14, 1999Date of Patent: September 18, 2001Assignee: Taiwan Semiconductor Manufacturing Co, Ltd.Inventors: Bor-Wen Chan, Yuan-Hung Liu
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Patent number: 6232175Abstract: A double recess crown-shaped DRAM capacitor is formed in a simplified process. A dielectric layer is formed over a substrate. Using photolithographic and etching techniques, a contact opening is formed in the dielectric layer. A conductive layer is formed over the dielectric layer filling the contact opening to form a conductive plug. A second dielectric layer is formed over the conductive layer. Again using photolithographic and etching techniques, the second dielectric layer is patterned to form a trapezoidal-shaped dielectric layer. An organic bottom anti-reflective coating (organic BARC) is coated over the trapezoidal-shaped dielectric layer and the conductive layer. Organic BARC above the trapezoidal-shaped dielectric layer is removed. Using the organic BARC as an etching mask, the trapezoidal-shaped dielectric layer is etched to form triangular-shaped dielectric layers and a trench in the conductive layer. The residual organic BARC is completely removed.Type: GrantFiled: December 17, 1999Date of Patent: May 15, 2001Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yuan-Hung Liu, Bor-Wen Chan
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Patent number: 6218244Abstract: A method of manufacturing a DRAM capacitor is described. A silicon substrate structure includes an oxide layer over a substrate and a polysilicon layer over the oxide layer. The polysilicon layer also includes a plug that penetrates the oxide layer. A patterned photoresist layer is next formed over the polysilicon layer. Spacers having a low etching rate are formed on the sidewalls of the photoresist layer by carrying out a chemical reaction next to the sidewall of the photoresist layer. A dry etching operation is carried out to etch the unreacted photoresist layer and the polysilicon layer exposed by the openings in the photoresist layer. Using the spacers as an etching mask, a portion of the polysilicon layer under the photoresist layer is removed by continuing the dry etching operation. Lastly, the spacers are removed to form a crown-shaped capacitor.Type: GrantFiled: January 13, 2000Date of Patent: April 17, 2001Assignee: Taiwan Semiconductor Mfg Co LtdInventors: Bor-Wen Chan, Yuan-Hung Liu
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Patent number: 6110837Abstract: The present invention discloses a method for forming hard mask of half critical dimension on a substrate. A substrate is provided for the base of integrated circuits. A silicon oxide layer is formed on the substrate. A photoresist layer is formed on the silicon oxide layer and it is has a critical dimension, which the conventional lithography process can make. Subsequently, a hard mask of half critical dimension is formed in the silicon oxide layer by using the photoresist layer as an etching mask. After the oxide hard mask is formed, the gate structure of half critical dimension is formed by using the oxide hard mask.Type: GrantFiled: April 28, 1999Date of Patent: August 29, 2000Assignee: Worldwide Semiconductor Manufacturing Corp.Inventors: Kung Linliu, Bor-Wen Chan