Patents by Inventor Borna Obradovic
Borna Obradovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230317822Abstract: Embodiments described herein may be related to transistor structures where dimpled spacers, which may also be referred to as inner spacers or offset spacers, may be formed around gates within an epitaxial structure such that the epitaxial material adjacent to the dimpled spacer is uniform and/or defect free. In embodiments, forming the dimpled spacers occurs after epitaxial growth. Other embodiments may be described and/or claimed.Type: ApplicationFiled: April 1, 2022Publication date: October 5, 2023Inventors: Stephen M. CEA, Borna OBRADOVIC, Rishabh MEHANDRU, Jack T. KAVALIEROS
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Patent number: 10181527Abstract: A field effect transistor (FET) structure includes: a gate; a first spacer having a first dielectric constant at a first region adjacent to the gate; and a second spacer having a second dielectric constant that is greater than the first dielectric constant at a second region adjacent to the gate.Type: GrantFiled: May 31, 2016Date of Patent: January 15, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Dharmendar Reddy Palle, Borna Obradovic, Joon Goo Hong, Mark Rodder
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Patent number: 9960232Abstract: A horizontal nanosheet field effect transistor (hNS FET) including source and drain electrodes, a gate electrode between the source and drain electrodes, a first spacer separating the source electrode from the gate electrode, a second spacer separating the drain electrode from the gate electrode, and a channel region under the gate electrode and extending between the source electrode and the drain electrode. The source electrode and the drain electrode each include an extension region. The extension region of the source electrode is under at least a portion of the first spacer and the extension region of the drain electrode is under at least a portion of the second spacer. The hNS FET also includes at least one layer of crystalline barrier material having a first thickness at the extension regions of the source and drain electrodes and a second thickness less than the first thickness at the channel region.Type: GrantFiled: November 1, 2016Date of Patent: May 1, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Borna Obradovic, Titash Rakshit, Mark Rodder
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Patent number: 9899529Abstract: A method for making a self-aligned vertical nanosheet field effect transistor. A vertical trench is etched in a layered structure including a plurality of layers, using reactive ion etching, and filled, using an epitaxial process, with a vertical semiconductor nanosheet. A sacrificial layer from among the plurality of layers is etched out and replaced with a conductive (e.g., metal) gate layer coated with a high-dielectric-constant dielectric material. Two other layers from among the plurality of layers, one above and one below the gate layer, are doped, and act as dopant donors for a diffusion process that forms two PN junctions in the vertical semiconductor nanosheet.Type: GrantFiled: June 28, 2016Date of Patent: February 20, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Joon Goo Hong, Borna Obradovic, Mark Rodder
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Patent number: 9870940Abstract: Methods of forming nanosheets for a semiconductor device are provided including providing a silicon on insulator (SOI) handle wafer, the SOT handle wafer including a silicon layer and a dielectric layer on the silicon layer; providing a first donor wafer; bonding the SOI handle wafer and the first donor wafer together to provide a bonded structure; debonding the bonded structure to provide an intermediate wafer including a plurality of silicon or non-silicon nanosheets and a plurality of dielectric layers alternately stacked; and bonding the intermediate wafer to a second donor wafer to provide a final wafer including a plurality of silicon or non-silicon layers and a plurality of dielectric layers alternately stacked, wherein the final wafer includes at least one more pair of silicon or non-silicon and dielectric layers than the intermediate wafer.Type: GrantFiled: March 10, 2016Date of Patent: January 16, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Wei-E Wang, Mark Rodder, Borna Obradovic
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Patent number: 9853114Abstract: A field effect transistor (FET) for an nFET and/or a pFET device including a fin having a stack of nanowire-like channel regions. The stack includes at least a first nanowire-like channel region and a second nanowire-like channel region stacked on the first nanowire-like channel region. The FET includes source and drain electrodes on opposite sides of the fin. The FET also includes a dielectric separation region including SiGe between the first and second nanowire-like channel regions extending completely from a surface of the second channel region facing the first channel region to a surface of the first channel region facing the second channel region. The FET includes a gate stack extending along a pair of sidewalls of the stack. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The metal layer does not extend between the first and second nanowire-like channel regions.Type: GrantFiled: March 14, 2017Date of Patent: December 26, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Mark S. Rodder, Borna Obradovic
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Publication number: 20170323941Abstract: A horizontal nanosheet field effect transistor (hNS FET) including source and drain electrodes, a gate electrode between the source and drain electrodes, a first spacer separating the source electrode from the gate electrode, a second spacer separating the drain electrode from the gate electrode, and a channel region under the gate electrode and extending between the source electrode and the drain electrode. The source electrode and the drain electrode each include an extension region. The extension region of the source electrode is under at least a portion of the first spacer and the extension region of the drain electrode is under at least a portion of the second spacer. The hNS FET also includes at least one layer of crystalline barrier material having a first thickness at the extension regions of the source and drain electrodes and a second thickness less than the first thickness at the channel region.Type: ApplicationFiled: November 1, 2016Publication date: November 9, 2017Inventors: Borna Obradovic, Titash Rakshit, Mark Rodder
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Patent number: 9805795Abstract: A non-volatile data retention circuit, which is configured to store complementary volatile charge states of an external latch, comprises a coupled giant spin hall latch configured to generate and store complementary non-volatile spin states corresponding to the complementary volatile charge states of the external latch in response to receiving a charge current from the external latch, and to generate a differential charge current signal corresponding to the complementary non-volatile spin states in response to application of a read voltage, a write switch coupled to the coupled giant spin hall latch and configured to selectively enable flow of the charge current from the external latch to the coupled giant spin hall latch in response to a sleep signal, and a read switch coupled to the coupled giant spin hall latch and to selectively enable the application of the read voltage to the coupled giant spin hall latch.Type: GrantFiled: September 14, 2016Date of Patent: October 31, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Titash Rakshit, Borna Obradovic
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Patent number: 9773904Abstract: A vertical field effect device includes a substrate and a vertical channel including InxGa1-xAs on the substrate. The vertical channel includes a pillar that extends from the substrate and includes opposing vertical surfaces. The device further includes a stressor layer on the opposing vertical surfaces of the vertical channel. The stressor layer includes a layer of epitaxial crystalline material that is epitaxially formed on the vertical channel and that has lattice constant in a vertical plane corresponding to one of the opposing vertical surfaces of the vertical channel that is greater than a corresponding lattice constant of the vertical channel.Type: GrantFiled: April 19, 2016Date of Patent: September 26, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Borna Obradovic, Chris Bowen, Titash Rakshit, Palle Dharmendar, Mark Rodder
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Publication number: 20170200499Abstract: A non-volatile data retention circuit, which is configured to store complementary volatile charge states of an external latch, comprises a coupled giant spin hall latch configured to generate and store complementary non-volatile spin states corresponding to the complementary volatile charge states of the external latch in response to receiving a charge current from the external latch, and to generate a differential charge current signal corresponding to the complementary non-volatile spin states in response to application of a read voltage, a write switch coupled to the coupled giant spin hall latch and configured to selectively enable flow of the charge current from the external latch to the coupled giant spin hall latch in response to a sleep signal, and a read switch coupled to the coupled giant spin hall latch and to selectively enable the application of the read voltage to the coupled giant spin hall latch.Type: ApplicationFiled: September 14, 2016Publication date: July 13, 2017Inventors: Titash Rakshit, Borna Obradovic
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Patent number: 9653287Abstract: A field effect transistor (FET) and a method to form the FET are disclosed. The FET comprises a channel region comprising a nanosheet layer/sacrificial layer stack. The stack comprises at least one nanosheet layer/sacrificial layer pair. Each nanosheet layer/sacrificial layer pair comprises an end surface. A conductive material layer is formed on the end surface of the pairs, and a source/drain contact is formed on the conductive material layer. In one embodiment, the sacrificial layer of at least one pair further may comprise a low-k dielectric material proximate to the end surface of the pair. A surface of the low-k dielectric material proximate to the end surface of the pair is in substantial alignment with the end surface of the nanosheet layer. Alternatively, the surface of the low-k dielectric material proximate to the end surface of the pair is recessed with respect to the end surface of the nanosheet layer.Type: GrantFiled: October 21, 2015Date of Patent: May 16, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Mark Rodder, Joon Hong, Jorge Kittl, Borna Obradovic
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Publication number: 20170133513Abstract: A method for making a self-aligned vertical nanosheet field effect transistor. A vertical trench is etched in a layered structure including a plurality of layers, using reactive ion etching, and filled, using an epitaxial process, with a vertical semiconductor nanosheet. A sacrificial layer from among the plurality of layers is etched out and replaced with a conductive (e.g., metal) gate layer coated with a high-dielectric-constant dielectric material. Two other layers from among the plurality of layers, one above and one below the gate layer, are doped, and act as dopant donors for a diffusion process that forms two PN junctions in the vertical semiconductor nanosheet.Type: ApplicationFiled: June 28, 2016Publication date: May 11, 2017Inventors: Joon Goo Hong, Borna Obradovic, Mark Rodder
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Patent number: 9647098Abstract: A field effect transistor (FET) includes a nanosheet stack having first and second stacked semiconductor channel layers. The first channel layer defines a channel region of a tunnel FET, and the second channel layer defines a channel region of a thermionic FET. Source and drain regions are provided on opposite sides of the nanosheet stack such that the first and second channel layers extend therebetween. A first portion of the source region adjacent the first channel layer and a second portion of the source region adjacent the second channel layer have opposite semiconductor conductivity types. Related fabrication and operating methods are also discussed.Type: GrantFiled: January 9, 2015Date of Patent: May 9, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Borna Obradovic, Robert C. Bowen, Dharmendar Reddy Palle, Mark S. Rodder
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Publication number: 20170110568Abstract: A field effect transistor (FET) structure includes: a gate; a first spacer having a first dielectric constant at a first region adjacent to the gate; and a second spacer having a second dielectric constant that is greater than the first dielectric constant at a second region adjacent to the gate.Type: ApplicationFiled: May 31, 2016Publication date: April 20, 2017Inventors: Dharmendar Reddy Palle, Borna Obradovic, Joon Goo Hong, Mark Rodder
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Publication number: 20170077304Abstract: A vertical field effect device includes a substrate and a vertical channel including InxGa1-xAs on the substrate. The vertical channel includes a pillar that extends from the substrate and includes opposing vertical surfaces. The device further includes a stressor layer on the opposing vertical surfaces of the vertical channel. The stressor layer includes a layer of epitaxial crystalline material that is epitaxially formed on the vertical channel and that has lattice constant in a vertical plane corresponding to one of the opposing vertical surfaces of the vertical channel that is greater than a corresponding lattice constant of the vertical channel.Type: ApplicationFiled: April 19, 2016Publication date: March 16, 2017Inventors: Borna Obradovic, Chris Bowen, Titash Rakshit, Palle Dharmendar, Mark Rodder
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Publication number: 20170040209Abstract: Methods of forming nanosheets for a semiconductor device are provided including providing a silicon on insulator (SOI) handle wafer, the SOT handle wafer including a silicon layer and a dielectric layer on the silicon layer; providing a first donor wafer; bonding the SOI handle wafer and the first donor wafer together to provide a bonded structure; debonding the bonded structure to provide an intermediate wafer including a plurality of silicon or non-silicon nano sheets and a plurality of dielectric layers alternately stacked; and bonding the intermediate wafer to a second donor wafer to provide a final wafer including a plurality of silicon or non-silicon layers and a plurality of dielectric layers alternately stacked, wherein the final wafer includes at least one more pair of silicon or non-silicon and dielectric layers than the intermediate wafer.Type: ApplicationFiled: March 10, 2016Publication date: February 9, 2017Inventors: Wei-E Wang, Mark Rodder, Borna Obradovic
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Patent number: 9466669Abstract: A semiconductor structure includes a first finFET device including a first fin, a first gate electrode structure on sidewalls and an upper surface of the first fin, a first channel region beneath the first gate electrode structure, and first source and drain regions in the first fin on opposite sides of the first channel region, and a second finFET device including a second fin, a second gate electrode structure on sidewalls and an upper surface of the second fin, a second channel region beneath the second gate electrode structure, and second source and drain regions in the second fin on opposite sides of the second channel region. The second gate electrode structure has a second physical gate length that is substantially the same as a first physical gate length of the first gate electrode structure, and the second finFET device has a second effective channel length that is different from a first effective channel length of the first gate electrode structure.Type: GrantFiled: April 10, 2015Date of Patent: October 11, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Mark S. Rodder, Borna Obradovic, Rwik Sengupta
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Publication number: 20160126310Abstract: A field effect transistor (FET) and a method to form the FET are disclosed. The FET comprises a channel region comprising a nanosheet layer/sacrificial layer stack. The stack comprises at least one nanosheet layer/sacrificial layer pair. Each nanosheet layer/sacrificial layer pair comprises an end surface. A conductive material layer is formed on the end surface of the pairs, and a source/drain contact is formed on the conductive material layer. In one embodiment, the sacrificial layer of at least one pair further may comprise a low-k dielectric material proximate to the end surface of the pair. A surface of the low-k dielectric material proximate to the end surface of the pair is in substantial alignment with the end surface of the nanosheet layer. Alternatively, the surface of the low-k dielectric material proximate to the end surface of the pair is recessed with respect to the end surface of the nanosheet layer.Type: ApplicationFiled: October 21, 2015Publication date: May 5, 2016Inventors: Mark RODDER, Joon HONG, Jorge KITTL, Borna OBRADOVIC
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Publication number: 20160111421Abstract: An integrated circuit comprises at least one block comprising a first cell and a second cell. The first cell comprises a first FET formed with a first contacted poly pitch (CPP), and the second cell comprises a second FET formed with a second CPP. The first CPP is greater than the second CPP. The first FET is part of a critical-speed path, and the second FET is part of a noncritical-speed path, in which the critical-speed path operates at a faster speed than the noncritical-speed path. The first FET and the second FET each comprise a planar FET, a finFET, a gate-all-around FET or a nanosheet FET. A method for forming the integrated circuit is also disclosed.Type: ApplicationFiled: August 17, 2015Publication date: April 21, 2016Inventors: Mark S. RODDER, Rwik SENGUPTA, Borna OBRADOVIC
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Patent number: 9287357Abstract: An integrated circuit may include multiple first, non-Si, nanosheet field-effect transistors (FETs) and multiple second, Si, nanosheet FETs. Nanosheets of ones of the first, non-Si, nanosheet FETs may include less than about 30% Si. The first, non-Si, nanosheet FETs may define a critical speed path of the circuit of the integrated circuit. Nanosheets of ones of the second, Si, nanosheet FETs may include more than about 30% Si. The second, Si, nanosheet FETs may define a non-critical speed path of the integrated circuit. Ones of the first, non-Si, nanosheet FETs may be configured to have a higher speed than a speed of ones of the second, Si, nanosheet FETs.Type: GrantFiled: June 11, 2015Date of Patent: March 15, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Mark S. Rodder, Borna Obradovic, Rwik Sengupta, Dharmendar Reddy Palle, Robert C. Bowen