Patents by Inventor Borna Obradovic
Borna Obradovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160020305Abstract: A field effect transistor (FET) includes a nanosheet stack having first and second stacked semiconductor channel layers. The first channel layer defines a channel region of a tunnel FET, and the second channel layer defines a channel region of a thermionic FET. Source and drain regions are provided on opposite sides of the nanosheet stack such that the first and second channel layers extend therebetween. A first portion of the source region adjacent the first channel layer and a second portion of the source region adjacent the second channel layer have opposite semiconductor conductivity types. Related fabrication and operating methods are also discussed.Type: ApplicationFiled: January 9, 2015Publication date: January 21, 2016Inventors: Borna Obradovic, Robert C. Bowen, Dharmendar Reddy Palle, Mark S. Rodder
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Publication number: 20150364542Abstract: An integrated circuit may include multiple first, non-Si, nanosheet field-effect transistors (FETs) and multiple second, Si, nanosheet FETs. Nanosheets of ones of the first, non-Si, nanosheet FETs may include less than about 30% Si. The first, non-Si, nanosheet FETs may define a critical speed path of the circuit of the integrated circuit. Nanosheets of ones of the second, Si, nanosheet FETs may include more than about 30% Si. The second, Si, nanosheet FETs may define a non-critical speed path of the integrated circuit. Ones of the first, non-Si, nanosheet FETs may be configured to have a higher speed than a speed of ones of the second, Si, nanosheet FETs.Type: ApplicationFiled: June 11, 2015Publication date: December 17, 2015Inventors: Mark S. RODDER, Borna OBRADOVIC, Rwik SENGUPTA, Dharmendar Reddy PALLE, Robert C. BOWEN
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Publication number: 20150318282Abstract: A semiconductor structure includes a first finFET device including a first fin, a first gate electrode structure on sidewalls and an upper surface of the first fin, a first channel region beneath the first gate electrode structure, and first source and drain regions in the first fin on opposite sides of the first channel region, and a second finFET device including a second fin, a second gate electrode structure on sidewalls and an upper surface of the second fin, a second channel region beneath the second gate electrode structure, and second source and drain regions in the second fin on opposite sides of the second channel region. The second gate electrode structure has a second physical gate length that is substantially the same as a first physical gate length of the first gate electrode structure, and the second finFET device has a second effective channel length that is different from a first effective channel length of the first gate electrode structure.Type: ApplicationFiled: April 10, 2015Publication date: November 5, 2015Inventors: Mark S. Rodder, Borna Obradovic, Rwik Sengupta
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Patent number: 8380476Abstract: Simulation of an electronic circuit including a model of a ferroelectric capacitor. The model of the ferroelectric capacitor includes a multi-domain ferroelectric capacitor, in which each of the domains is associated with a positive and a negative coercive voltage. A probability distribution function of positive and negative coercive voltages is defined, from which a weighting function of the distribution of domains having those coercive voltages is defined. To create a model of a small ferroelectric capacitor, a Poisson probability distribution is assigned to each of an array of gridcells defining the probability distribution function of positive and negative coercive voltages, and a number of domains assigned to each gridcell is randomly selected according to that Poisson distribution and an expected number of domains in the modeled capacitor for that gridcell, based on the area of the modeled capacitor.Type: GrantFiled: September 29, 2009Date of Patent: February 19, 2013Assignee: Texas Instruments IncorporatedInventors: Borna Obradovic, Keith R. Green, Scott R. Summerfelt
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Publication number: 20120168837Abstract: A ferroelectric apparatus includes a circuit having a first capacitor electrically coupled to a plate line via a top terminal connection of the first ferroelectric capacitor and to a storage node via a bottom terminal connection of the first ferroelectric capacitor. The circuit also includes a second ferroelectric capacitor electrically coupled to a second plate line via a second bottom terminal connection of the second ferroelectric capacitor and to the storage node via a second top terminal connection of the second ferroelectric capacitor.Type: ApplicationFiled: December 6, 2011Publication date: July 5, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven Craig BARTLING, Michael Patrick CLINTON, Borna OBRADOVIC
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Patent number: 8170858Abstract: Simulation of an electronic circuit including a model of a ferroelectric capacitor. The model of the ferroelectric capacitor includes a multi-domain ferroelectric capacitor, in which each of the domains is associated with a positive and a negative coercive voltage. A probability distribution function of positive and negative coercive voltages is defined, from which a weighting function of the distribution of domains having those coercive voltages is defined. The electrical behavior of the ferroelectric capacitor is evaluated by evaluating the polarization of each of the domains, as weighted by the weighting function. A time-dependent factor can be included in the polarization expression evaluated for each domain, to include the effect of relaxation. The effects of longer-term mechanisms, such as imprint, can be modeled by deriving a probability distribution function for the domains after an accelerated stress.Type: GrantFiled: February 27, 2009Date of Patent: May 1, 2012Assignee: Texas Instruments IncorporatedInventors: Borna Obradovic, Keith Green
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Patent number: 8119470Abstract: Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics.Type: GrantFiled: March 21, 2007Date of Patent: February 21, 2012Assignee: Texas Instruments IncorporatedInventors: Shashank Sureshchandra Ekbote, Borna Obradovic, Lindsey Hall, Craig Huffman, Ajith Varghese
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Patent number: 8114729Abstract: A method of fabricating a CMOS integrated circuit and integrated circuits therefrom includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon including layer on the gate dielectric. A portion of the polysilicon layer is masked, and pre-gate etch implant of a first dopant type into an unmasked portion of the polysilicon layer is performed, wherein masked portions of the polysilicon layer are protected from the first dopant. The polysilicon layer is patterned to form a plurality of polysilicon gates and a plurality of polysilicon lines, wherein the masked portion includes at least one of the polysilicon lines which couple a polysilicon gate of a PMOS device to a polysilicon gate of an NMOS device.Type: GrantFiled: October 10, 2007Date of Patent: February 14, 2012Assignee: Texas Instruments IncorporatedInventors: Shashank Ekbote, Kamel Benaissa, Greg C. Baldwin, Borna Obradovic
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Publication number: 20110282639Abstract: A non-quasi-static model of the programming behavior of a floating-gate metal-oxide-semiconductor (MOS) transistor. This model is based on evaluation of a body current, for example determined as a function of voltages applied to the transistor from the circuit environment. The body current is used as an input to a non-quasi-static function on which the modeled gate injection current is based. In one example, the body current is applied to a representation of a series R-C circuit beginning from a time corresponding to the onset of avalanche breakdown, with the voltage across the capacitor serving as a control voltage of a voltage-controlled current source that drives the gate injection current. Integration of the gate injection current over the time interval of the programming pulse provides an estimate of the trapped charge at the floating gate.Type: ApplicationFiled: January 13, 2011Publication date: November 17, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Borna Obradovic, Keith Green
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Patent number: 7892930Abstract: A method of forming a transistor device is provided wherein a gate structure is formed over a semiconductor body of a first conductivity type. The gate structure is formed comprising a protective cap thereover and defining source/drain regions laterally adjacent thereto. A first implant is performed of a second conductivity type into both the gate structure and the source/drain regions. The semiconductor body is etched to form recesses substantially aligned to the gate structure wherein the first implant is removed from the source/drain regions. Source/drain regions are implanted or grown by a selective epitaxial growth.Type: GrantFiled: October 8, 2007Date of Patent: February 22, 2011Assignee: Texas Instruments IncorporatedInventors: Borna Obradovic, Shashank S. Ekbote
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Publication number: 20110027954Abstract: A method of forming a transistor device is provided wherein a gate structure is formed over a semiconductor body of a first conductivity type. The gate structure is formed comprising a protective cap thereover and defining source/drain regions laterally adjacent thereto. A first implant is performed of a second conductivity type into both the gate structure and the source/drain regions. The semiconductor body is etched to form recesses substantially aligned to the gate structure wherein the first implant is removed from the source/drain regions. Source/drain regions are implanted or grown by a selective epitaxial growth.Type: ApplicationFiled: October 8, 2010Publication date: February 3, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Borna Obradovic, Shashank S. Ekbote
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Publication number: 20100299115Abstract: Simulation of an electronic circuit including a model of a ferroelectric capacitor. The model of the ferroelectric capacitor includes a multi-domain ferroelectric capacitor, in which each of the domains is associated with a positive and a negative coercive voltage. A probability distribution function of positive and negative coercive voltages is defined, from which a weighting function of the distribution of domains having those coercive voltages is defined. To create a model of a small ferroelectric capacitor, a Poisson probability distribution is assigned to each of an array of gridcells defining the probability distribution function of positive and negative coercive voltages, and a number of domains assigned to each gridcell is randomly selected according to that Poisson distribution and an expected number of domains in the modeled capacitor for that gridcell, based on the area of the modeled capacitor.Type: ApplicationFiled: September 29, 2009Publication date: November 25, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Borna Obradovic, Keith R. Green, Scott R. Summerfelt
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Patent number: 7812401Abstract: An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a gate insulator over the channel region. A silicide layer forming a low resistance contact is at an interface region at a surface portion of the source and drain. At the interface region a chemical concentration of the first dopant is at least 5×1020 cm?3. Silicide interfaces according to the invention provide MOS transistor with a low silicide interface resistance, low pipe density, with an acceptably small impact on short channel behavior.Type: GrantFiled: January 18, 2010Date of Patent: October 12, 2010Assignee: Texas Instruments IncorporatedInventors: Borna Obradovic, Shashank Ekbote, Mark Visokay
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Publication number: 20100174513Abstract: Simulation of an electronic circuit including a model of a ferroelectric capacitor. The model of the ferroelectric capacitor includes a multi-domain ferroelectric capacitor, in which each of the domains is associated with a positive and a negative coercive voltage. A probability distribution function of positive and negative coercive voltages is defined, from which a weighting function of the distribution of domains having those coercive voltages is defined. The electrical behavior of the ferroelectric capacitor is evaluated by evaluating the polarization of each of the domains, as weighted by the weighting function. A time-dependent factor can be included in the polarization expression evaluated for each domain, to include the effect of relaxation. The effects of longer-term mechanisms, such as imprint, can be modeled by deriving a probability distribution function for the domains after an accelerated stress.Type: ApplicationFiled: February 27, 2009Publication date: July 8, 2010Applicant: Texas Instruments IncorporatedInventors: Borna Obradovic, Keith Green
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Patent number: 7727838Abstract: A method of forming an integrated circuit includes forming a gate structure over a semiconductor body, and forming a shadowing structure over the semiconductor body laterally spaced from the gate structure, thereby defining an active area in the semiconductor body therebetween. The method further includes performing an angled implant into the gate structure, wherein the shadowing structure substantially blocks dopant from the angled implant from implanting into the active area, and performing a source/drain implant into the gate structure and the active area.Type: GrantFiled: July 27, 2007Date of Patent: June 1, 2010Assignee: Texas Instruments IncorporatedInventors: Borna Obradovic, Shashank S. Ekbote
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Patent number: 7718482Abstract: A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon layer on the gate dielectric layer. The polysilicon layer is patterned while being undoped to form a plurality of polysilicon comprising gates. A first pattern is used to protect a plurality of PMOS devices and a first n-type implant is performed to dope the gates and source/drain regions for a plurality of NMOS devices. A second pattern is used to protect the PMOS devices and the sources/drains and gates for a portion of the plurality of NMOS devices and a second n-type implant is performed to dope the gates of the other NMOS devices.Type: GrantFiled: October 30, 2007Date of Patent: May 18, 2010Assignee: Texas Instruments IncorporatedInventors: Shashank Ekbote, Borna Obradovic, Greg C. Baldwin
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Publication number: 20100109089Abstract: An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a gate insulator over the channel region. A silicide layer forming a low resistance contact is at an interface region at a surface portion of the source and drain. At the interface region a chemical concentration of the first dopant is at least 5×1020 cm?3. Silicide interfaces according to the invention provide MOS transistor with a low silicide interface resistance, low pipe density, with an acceptably small impact on short channel behavior.Type: ApplicationFiled: January 18, 2010Publication date: May 6, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Borna OBRADOVIC, Shashank EKBOTE, Mark VISOKAY
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Patent number: 7682892Abstract: An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a gate insulator over the channel region. A silicide layer forming a low resistance contact is at an interface region at a surface portion of the source and drain. At the interface region a chemical concentration of the first dopant is at least 5×1020 cm?3. Silicide interfaces according to the invention provide MOS transistor with a low silicide interface resistance, low pipe density, with an acceptably small impact on short channel behavior.Type: GrantFiled: August 31, 2007Date of Patent: March 23, 2010Assignee: Texas Instruments IncorporatedInventors: Borna Obradovic, Shashank Ekbote, Mark Visokay
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Patent number: 7572716Abstract: A method is disclosed for doping a target area of a semiconductor substrate, such as a source or drain region of a transistor, with an electronically active dopant (such as an N-type dopant used to create active areas in NMOS devices, or a P-type dopant used to create active areas in PMOS devices) having a well-controlled placement profile and strong activation. The method comprises placing a carbon-containing diffusion suppressant in the target area at approximately 50% of the concentration of the dopant, and activating the dopant by an approximately 1,040 degree Celsius thermal anneal. In many cases, a thermal anneal at such a high temperature induces excessive diffusion of the dopant out of the target area, but this relative concentration of carbon produces a heretofore unexpected reduction in dopant diffusion during such a high-temperature thermal anneal.Type: GrantFiled: April 25, 2007Date of Patent: August 11, 2009Assignee: Texas Instruments IncorporatedInventors: Haowen Bu, Shashank S. Ekbote, Borna Obradovic, Srinivasan Chakravarthi
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Patent number: 7537988Abstract: A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric and a plurality of gate electrodes thereon in both NMOS and PMOS regions using the surface. A multi-layer offset spacer stack including a top layer and a compositionally different bottom layer is formed and the multi-layer spacer stack is etched to form offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize a thinner offset spacer are covered with a first masking material, and transistors designed to utilize a thicker offset spacer are patterned and first implanted. At least a portion of the top layer is removed to leave the thinner offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize the thicker offset spacer are covered with a second masking material, and the transistors designed to utilize the thinner offset spacer are patterned and second implanted.Type: GrantFiled: October 10, 2007Date of Patent: May 26, 2009Assignee: Texas Instruments IncorporatedInventors: Shashank Ekbote, Deborah J. Riley, Borna Obradovic