Patents by Inventor Bo-Ting Chen

Bo-Ting Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12265412
    Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.
    Type: Grant
    Filed: April 11, 2024
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Neng Chen, Yen-Lin Liu, Chia-Wei Hsu, Jo-Yu Wu, Chang-Fen Hu, Shao-Yu Li, Bo-Ting Chen
  • Publication number: 20250012844
    Abstract: A built-in self-tester (BIST) of a semiconductor device including: an input/output (I/O) circuit including an output buffer and an input buffer, an output of the output buffer being coupled at an I/O terminal to an input of the input buffer, the I/O terminal being configured to receive or provide an external I/O signal; one or more resistive-network cell regions arranged to affect a reference current received at the I/O terminal; and a switching arrangement configured to selectively couple the one or more resistive-network cell regions alternatively to a first reference voltage during a first phase or a second reference voltage during a second phase, the switching arrangement being further configured to determine electrostatic discharge (ESD) damage to metal-oxide-semiconductor (MOS) transistors included in the semiconductor device based on (1) phase and (2) an output signal of the input buffer
    Type: Application
    Filed: July 25, 2023
    Publication date: January 9, 2025
    Inventors: Huan-Neng CHEN, Bo-Ting CHEN, Shao-Yu LI, Chung-Lun HONG, Cun Cun CHEN
  • Publication number: 20240387515
    Abstract: An integrated circuit (IC) device includes a substrate having a front side, a back side below the front side, and first functional circuitry and a first electrostatic discharge (ESD) clamp circuit on the front side of the substrate. The IC device further includes a first connection tower that extends below the back side of the substrate and is connected to an input/output pad below the back side of the substrate, and one or more first front side conductors and one or more first front side vias which connect the first buried connection tower to the first functional circuitry and to the first ESD clamp circuit.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Chia-Wei HSU, Bo-Ting CHEN, Jam-Wem LEE
  • Patent number: 12148746
    Abstract: An integrated circuit (IC) device includes a semiconductor substrate, a first connection tower, and one or more first front side conductors and one or more first front side metal vias. The semiconductor substrate includes a first semiconductor substrate segment having first functional circuitry and a second semiconductor substrate segment having a first electrostatic discharge (ESD) clamp circuit. The first connection tower connects to an input/output pad. The one or more first front side conductors and one or more first front side metal vias connect the first buried connection tower to the first functional circuitry in the first semiconductor substrate segment and to the first ESD clamp circuit in the second semiconductor substrate segment.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Wei Hsu, Bo-Ting Chen, Jam-Wem Lee
  • Publication number: 20240371925
    Abstract: A semiconductor device includes a semiconductor substrate having a first protected circuit; a first guard ring; and a second guard ring adjacent to the first guard ring and around the first protected circuit. The second guard ring includes a first via tower configured to provide a first reference voltage; a second via tower configured to provide a second reference voltage different than the first reference voltage; and at least a third via tower configured to provide the first reference voltage.
    Type: Application
    Filed: July 12, 2024
    Publication date: November 7, 2024
    Inventors: Chia-Wei HSU, Bo-Ting CHEN, Jam-Wem LEE
  • Patent number: 12100732
    Abstract: A method of fabricating a semiconductor device includes forming a semiconductor substrate having a first protected circuit, and forming a first guard ring around the first protected circuit including: forming a first wall configured to provide a first reference voltage; and forming a second wall configured to provide a second reference voltage different than the first reference voltage.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: September 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Chia-Wei Hsu, Bo-Ting Chen, Jam-Wem Lee
  • Publication number: 20240267044
    Abstract: Circuits and methods for preventing glitch in a circuit are disclosed. In one example, a circuit coupled to an input/output pad is disclosed. The circuit includes: a first level shifter, a second level shifter, and a control logic circuit. The first level shifter is configured for generating a data signal. The second level shifter is configured for generating an output enable signal. The first and second level shifters are controlled by first and second power-on-control signals, respectively. The control logic circuit is coupled to the first level shifter and the second level shifter.
    Type: Application
    Filed: April 16, 2024
    Publication date: August 8, 2024
    Inventors: Tsung-Hsin YU, Nick PAI, Bo-Ting CHEN
  • Publication number: 20240255977
    Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.
    Type: Application
    Filed: April 11, 2024
    Publication date: August 1, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Neng CHEN, Yen-Lin LIU, Chia-Wei HSU, Jo-Yu WU, CHANG-FEN HU, Shao-Yu LI, Bo-Ting CHEN
  • Patent number: 11984883
    Abstract: Circuits and methods for preventing glitch in a circuit are disclosed. In one example, a circuit coupled to an input/output pad is disclosed. The circuit includes: a first level shifter, a second level shifter, and a control logic circuit. The first level shifter is configured for generating a data signal. The second level shifter is configured for generating an output enable signal. The first and second level shifters are controlled by first and second power-on-control signals, respectively. The control logic circuit is coupled to the first level shifter and the second level shifter.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsin Yu, Nick Pai, Bo-Ting Chen
  • Patent number: 11966241
    Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Neng Chen, Yen-Lin Liu, Chia-Wei Hsu, Jo-Yu Wu, Chang-Fen Hu, Shao-Yu Li, Bo-Ting Chen
  • Patent number: 11916548
    Abstract: A buffer circuit includes an input terminal configured to receive an input signal, an output terminal, an inverter, and a resistor-capacitor (RC) circuit coupled in series with the inverter between the input terminal and the output terminal. The RC circuit includes an NMOS transistor coupled between an RC circuit output terminal and a reference node, a resistor coupled between the RC circuit output terminal and a power supply node, and a capacitor coupled between the RC circuit output terminal and one of the power supply node or the reference node, and the inverter and the RC circuit are configured to generate an output signal at the output terminal based on the input signal.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yen Lin, Yuan-Ju Chan, Bo-Ting Chen
  • Publication number: 20240063213
    Abstract: A method of protecting a device (protected device) (in a semiconductor system from an electrostatic discharge (ESD)) includes: coupling the protected device between a first node and a first reference voltage; coupling an ESD device between the first node and the first reference voltage; and selectively and actively coupling an input of the ESD device to a second reference voltage thereby selectively and actively turning on the ESD device.
    Type: Application
    Filed: October 16, 2023
    Publication date: February 22, 2024
    Inventors: Wan-Yen LIN, Bo-Ting CHEN
  • Publication number: 20240055424
    Abstract: A semiconductor structure includes a substrate and a stack of p-n junction structures embedded in the substrate. The semiconductor structure includes a semiconductor fin protruding from the substrate. The semiconductor structure includes a pair of source/drain structures disposed in the semiconductor fin. The semiconductor structure includes a gate structure over a channel region of the semiconductor fin and interposed between the pair of source/drain structures.
    Type: Application
    Filed: February 7, 2023
    Publication date: February 15, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Zi-Ang Su, Bo-Ting Chen, Chung-Sheng Yuan, Yi-Kan Cheng
  • Patent number: 11791329
    Abstract: A method of protecting a device (protected device) in a semiconductor system from an electrostatic discharge (ESD), the protected device being coupled between a first node and a first reference voltage, the method including: coupling an ESD device between the first node and the first reference voltage; coupling a shunting device between an input of the protected device and the first reference voltage; coupling a feedback control circuit between the first node and an input of the shunting device; and using the shunting device to actively couple the input of the protected device to the first reference voltage.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yen Lin, Bo-Ting Chen
  • Publication number: 20230215861
    Abstract: An electro-static discharge (ESD) protection network for an input/output (I/O) pad includes a driver stack including an upper branch and a lower branch, the upper branch being electrically connected between a first node that has a first reference voltage and the I/O pad, and the lower branch being electrically connected between the I/O pad and a second node that has a second reference voltage; a first ESD device electrically connected between the I/O pad and a third node that has a third reference voltage; and a power clamp between the third node and the second node.
    Type: Application
    Filed: May 2, 2022
    Publication date: July 6, 2023
    Inventors: Chia-Hui CHEN, Chia-Jung CHANG, Bo-Ting CHEN
  • Publication number: 20230107156
    Abstract: A buffer circuit includes an input terminal configured to receive an input signal, an output terminal, an inverter, and a resistor-capacitor (RC) circuit coupled in series with the inverter between the input terminal and the output terminal. The RC circuit includes an NMOS transistor coupled between an RC circuit output terminal and a reference node, a resistor coupled between the RC circuit output terminal and a power supply node, and a capacitor coupled between the RC circuit output terminal and one of the power supply node or the reference node, and the inverter and the RC circuit are configured to generate an output signal at the output terminal based on the input signal.
    Type: Application
    Filed: December 9, 2022
    Publication date: April 6, 2023
    Inventors: Wan-Yen LIN, Yuan-Ju CHAN, Bo-Ting CHEN
  • Patent number: 11600613
    Abstract: A protection cell for a cell library. The protection cell defines a protection circuit for an IC having a driving device with a first supply voltage Vdd1 and an output, and a driven device having an input and a second supply voltage Vdd2. The protection circuit includes a first device from the group consisting of a P-diode and a gate-Vdd PMOS. The first device is coupled between a first power bus connected to Vdd2 and the input of the driven device. The input of the driven device is coupled by way of a resistor to the output of the driving device. A second device corresponding to the first device is provided, from the group consisting of an N-diode and a grounded gate NMOS. The second device is coupled between the input of the driven device and a ground bus.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: March 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Bo-Ting Chen
  • Publication number: 20230068882
    Abstract: An integrated circuit (IC) device includes a semiconductor substrate, a first connection tower, and one or more first front side conductors and one or more first front side metal vias. The semiconductor substrate includes a first semiconductor substrate segment having first functional circuitry and a second semiconductor substrate segment having a first electrostatic discharge (ESD) clamp circuit. The first connection tower connects to an input/output pad. The one or more first front side conductors and one or more first front side metal vias connect the first buried connection tower to the first functional circuitry in the first semiconductor substrate segment and to the first ESD clamp circuit in the second semiconductor substrate segment.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Chia-Wei HSU, Bo-Ting CHEN, Jam-Wem LEE
  • Publication number: 20230064525
    Abstract: A method of fabricating a semiconductor device includes forming a semiconductor substrate having a first protected circuit, and forming a first guard ring around the first protected circuit including: forming a first wall configured to provide a first reference voltage; and forming a second wall configured to provide a second reference voltage different than the first reference voltage.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Chia-Wei HSU, Bo-Ting CHEN, Jam-Wem LEE
  • Publication number: 20230009027
    Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.
    Type: Application
    Filed: February 11, 2022
    Publication date: January 12, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Neng Chen, Yen-Lin LIU, Chia-Wei Hsu, Jo-Yu Wu, CHANG-FEN HU, Shao-Yu Li, Bo-Ting Chen