Abstract: A data processing system, apparatus and method for performing fractional multiply operations is disclosed. The system includes a memory that stores instructions for SIMD operations and a processing core. The processing core includes registers that store operands for the fractional multiply operations. A coprocessor included in the processing core performs the fractional multiply operations on the operands and stores the result in a destination register that is also included in the processing core.

Abstract: According to some embodiments, a technique provides for the execution of an instruction that includes receiving residual data of a first image and decoded pixels of a second image, zero-extending a plurality of unsigned data operands of the decoded pixels producing a plurality of unpacked data operands, adding a plurality of signed data operands of the residual data to the plurality of unpacked data operands producing a plurality of signed results; and saturating the plurality of signed results producing a plurality of unsigned results.

Abstract: According to some embodiments, a dual multiply-accumulate operation optimized for even and odd multisample calculations is disclosed.

Abstract: A device for capturing image data includes a first image sensor. A first interface receives the image data from the first image sensor based on a first synchronization signal. The first interface has a first mode that is associated with receiving the first synchronization signal from the first image sensor and a second mode that is associated with sending the first synchronization signal to the first image sensor.

Abstract: A system and method of adaptive edge detection and noise reduction in an image where edge information is detected for each color component of each pixel, whether sensed or synthesized. In some embodiments, the filter applied to a selected non-edge pixel may be determined by the ultimate size of a region around the selected pixel, where the size of the region may be increased if a count of the non-edge pixels in the region is less than a threshold value.

Abstract: Methods and apparatus for calculating Single-Instruction-Multiple-Data (SIMD) complex arithmetic. A coprocessor instruction has a format identifying a multiply and subtract instruction to generate real components for complex multiplication of first operand complex data and corresponding second operand complex data, a cross multiply and add instruction to generate imaginary components for complex multiplication of the first operand complex data and the corresponding second operand complex data, an add-subtract instruction to add real components of the first operand to imaginary components of the second operand and to subtract real components of the second operand from imaginary components of the first operand, and a subtract-add instruction to subtract the imaginary components of the second operand from the real components of the first operand and to add the real components of the second operand to the imaginary components of the first operand.

Abstract: A data processing system, apparatus and method for performing fractional multiply operations is disclosed. The system includes a memory that stores instructions for SIMD operations and a processing core. The processing core includes registers that store operands for the fractional multiply operations. A coprocessor included in the processing core performs the fractional multiply operations on the operands and stores the result in a destination register that is also included in the processing core.

Abstract: A computer-implemented method for noise management in a digital image system measures noise levels of pixel data. The noise levels are adjusted with at least one of an intensity gain setting, a spatial gain setting, and a global gain setting to calculate noise adaptive thresholds for use during spatial processing of the pixel data.

Abstract: According to some embodiments, a Single-Instruction/Multiple-Data (SIMD) averaging instruction is used to process pixels of image data. The averaging instruction generates a set of four-pixel averages, where each average is generated from two pixels in a first source register and two pixels in a second source register. The first source register contains a plurality of pixels from a first row of pixels and the second source register contains a plurality of pixels from a second row. In one embodiment, the first and second rows are adjacent rows in an image and the averaging instruction is used, for example, to down-scale an image, perform color conversion, and the like. In another embodiment, the first and second rows are from different images and the averaging instruction is used, for example, in motion estimation for video encoding, in motion compensation for video decoding, and the like.

Abstract: Methods and apparatus for calculating Single-Instruction-Multiple-Data (SIMD) complex arithmetic. A coprocessor instruction has a format identifying a multiply and subtract instruction to generate real components for complex multiplication of first operand complex data and corresponding second operand complex data, a cross multiply and add instruction to generate imaginary components for complex multiplication of the first operand complex data and the corresponding second operand complex data, an add-subtract instruction to add real components of the first operand to imaginary components of the second operand and to subtract real components of the second operand from imaginary components of the first operand, and a subtract-add instruction to subtract the real components of the second operand from the imaginary components of the first operand and to add the real components of the first operand to the imaginary components of the second operand.

Abstract: A method and apparatus for calculation and storage of Single-Instruction-Multiple-Data (SIMD) saturation history information. A first coprocessor instruction has a first format identifying a saturation operation, a first source having packed data elements and a second source having packed data elements. The saturating operation is executed on the packed data elements of the first and second sources. Saturation flags are stored in the Wireless Coprocessor Saturation Status Flag (wCSSF) register to indicate if a result of the saturating operation saturated. A second coprocessor instruction has a second format identifying a saturation history processing operation and a saturation data size. An operand for the processing operation is determined based on the saturation data size, and the processing operation is executed on the saturation flags and the operand for the saturation data size. Condition code flags are stored in a status register to indicate the result of processing operation.

Abstract: According to some embodiments, a dual multiply-accumulate operation optimized for even and odd multisample calculations is disclosed.

Abstract: A system includes an image sensor and an interface to receive image data from the image sensor. The interface selects between providing at least one synchronization signal to the image sensor and receiving the synchronization signal(s) from the image sensor. The synchronization signal(s) are associated with the communication of the image data from the image sensor.

Abstract: Methods and apparatus for calculating Single-Instruction-Multiple-Data (SIMD) complex arithmetic. A coprocessor instruction has a format identifying a multiply and subtract instruction to generate real components for complex multiplication of first operand complex data and corresponding second operand complex data, a cross multiply and add instruction to generate imaginary components for complex multiplication of the first operand complex data and the corresponding second operand complex data, an add-subtract instruction to add real components of the first operand to imaginary components of the second operand and to subtract real components of the second operand from imaginary components of the first operand, and a subtract-add instruction to subtract the real components of the second operand from the imaginary components of the first operand and to add the real components of the first operand to the imaginary components of the second operand.

Abstract: A method and apparatus for calculation and storage of Single-Instruction-Multiple-Data (SIMD) saturation history information. A first coprocessor instruction has a first format identifying a saturating operation, a first source having packed data elements and a second source having packed data elements. The saturating operation is executed on the packed data elements of the first and second sources. Saturation flags are stored in the Wireless Coprocessor Saturation Status Flag (wCSSF) register to indicate if a result of the saturating operation saturated. A second coprocessor instruction has a second format identifying a saturation history processing operation and a saturation data size. An operand for the processing operation is determined based on the saturation data size, and the processing operation is executed on the saturation flags and the operand for the saturation data size. Condition code flags are stored in a status register to indicate the result of processing operation.

Abstract: According to some embodiments, a dual multiply-accumulate operation optimized for even and odd multisample calculations is disclosed.

Abstract: According to some embodiments, a Single-Instruction/Multiple-Data averaging operation is presented. The averaging operation averages multiple sets of data elements, for example, two data elements each from a first source and a second source, producing a set of averages. In at least one embodiment, in a first adder stage, a first plurality of data elements are added to a second plurality of data elements, generating a plurality of intermediate results. In a second adder stage, multiple different combinations of the plurality of intermediate results are added together, generating a plurality of sum results. The two least significant bits of each sum result are discarded.

Abstract: A method and apparatus for calculation and storage of Single-Instruction-Multiple-Data (SIMD) saturation history information pursuant to instruction execution. A coprocessor instruction has a format identifying a saturating operation, a first source having packed data elements and a second source having packed data elements. The saturating operation is executed on the packed data elements of the first and second sources. Saturation flags are stored in bits zero through seven of the Wireless Coprocessor Saturation Status Flag (wCSSF) register to indicate if a result of the saturating operation saturated.

Abstract: Plural sum of absolute difference devices are used to calculate distortions between specified parts of specified images in a video stream. The video can be from a video camera, or other device.

Abstract: A register file architecture in a general purpose digital signal processor (DSP) supports alignment independent SIMD (Single Instruction/Multiple Data) operations. The register file architecture includes a register pair and an alignment multiplexer. Two 32 bit grouped words may be loaded into the register pair. Each grouped word includes four 8 bit operands. The alignment state of the 32 bit words may be determined by the two least significant bits (LSBs) of the pointer addresses of the grouped words. These LSBs are used to control the alignment MUX to select n operands from the two 32 bit grouped words and output an aligned 32 bit grouped word to execution units for parallel processing.