Abstract: In one embodiment, a digital signal processor (DSP) processes both n-bit data and (n/2)-bit data. The DSP includes multiple processing paths. A first processing path processes n-bit data. A second processing path is processes (n/2)-bit data. The multiple processing paths may be established using multiple components or may share components. When the processing paths share components, only one of the processing paths may be used at a time.

Abstract: An image processor that calculates values that are related to distortion between two image parts. The values are detected in a previous calculation. Those values are then used in the next calculation cycle to detect an early exit. That value, called least, divided by the number of accumulators, and its negative is loaded into the accumulators. When the accumulators reach zero, an early exit is established.

Abstract: Images are obtained for image compression. The images are compared using sum of absolute difference devices, which have arithmetic parts, and accumulators. The sign bits of the accumulators are determined at a time of minimum distortion between two images. These sign bits are associated with sets of probabilistically-similar parts. When other sets from that set are obtained later, an early exit is established.

Abstract: In one embodiment, a digital-signal processor (DSP) is described for multi-level global accumulation. The DSP includes a plurality of absolute difference determinators in a first stage. The absolute difference determinators may include arithmetic logic-units (ALUS) in combination with multiplexers. By using multiple absolute difference determinators, the throughput of the DSP is increased. An existing multiplier may be reconfigured into an adder tree to process the absolute difference results obtained in the first stage. To further increase, throughput, multiple DSPs with multiple absolute difference determinators may be operated in parallel.

Abstract: In one embodiment, a digital signal processor (DSP) processes both n-bit data and (n/2)-bit data. The DSP includes multiple processing paths. A first processing path processes n-bit data. A second processing path is processes (n/2)-bit data. The multiple processing paths may be established using multiple components or may share components. When the processing paths share components, only one of the processing paths may be used at a time.

Abstract: An image processor that calculates values that are related to distortion between two image parts. The values are detected in a previous calculation. Those values are then used in the next calculation cycle to detect an early exit. That value, called least, divided by the number of accumulators, and its negative is loaded into the accumulators. When the accumulators reach zero, an early exit is established.

Abstract: A system includes an image sensor and an interface to receive image data from the image sensor. The interface selects between providing at least one synchronization signal to the image sensor and receiving the synchronization signal(s) from the image sensor. The synchronization signal(s) are associated with the communication of the image data from the image sensor.

Abstract: Plural sum of absolute difference devices are used to calculate distortions between specified parts of specified images in a video stream. The video can be from a video camera, or other device.

Abstract: An integrated circuit which has two separate paths for two different data widths. The first processing path processes data up to n bits in a n multiplier. A second path operates in parallel with the first path, and includes smaller units which process data up to n 2 bits. The two paths can operate in parallel, but since the two paths have different data widths, they can more effectively operate with the different data sizes.

Abstract: In one embodiment, a digital-signal processor (DSP) is described for multi-level global accumulation. The DSP includes a plurality of absolute difference determinators in a first stage. The absolute difference determinators may include arithmetic logic-units (ALUS) in combination with multiplexers. By using multiple absolute difference determinators, the throughput of the DSP is increased. An existing multiplier may be reconfigured into an adder tree to process the absolute difference results obtained in the first stage. To further increase, throughput, multiple DSPs with multiple absolute difference determinators may be operated in parallel.

Abstract: An image processor that calculates values that are related to distortion between two image parts. The values are detected in a previous calculation. Those values are then used in the next calculation cycle to detect an early exit. That value, called least, divided by the number of accumulators, and its negative is loaded into the accumulators. When the accumulators reach zero, an early exit is established.

Abstract: A method and apparatus for calculation and storage of Single-Instruction-Multiple-Data (SIMD) saturation history information pursuant to instruction execution. A coprocessor instruction has a format identifying a saturating operation, a first source having packed data elements and a second source having packed data elements. The saturating operation is executed on the packed data elements of the first and second sources. Saturation flags are stored in bits zero through seven of the Wireless Coprocessor Saturation Status Flag (wCSSF) register to indicate if a result of the saturating operation saturated.

Abstract: Plural sum of absolute difference devices are used to calculate distortions between specified parts of specified images in a video stream. The video can be from a video camera, or other device.

Abstract: An adaptive color depth control may receive input signals from a power mode block, an ambient light sensor and/or a resource usage monitor to adjust the performance of a system through adaptation of the number of bits-per-pixel for each of the three primary colors supplied to a display. The spatial resolution may be adapted in a similar manner with inputs from the power mode block, ambient light sensor, and/or resource usage monitor.

Abstract: In one embodiment, a digital signal processor (DSP) is described for multi-level global accumulation. The DSP includes a plurality of absolute difference determinators in a first stage. The absolute difference determinators may include arithmetic logic units (ALUs) in combination with multiplexers. By using multiple absolute difference determinators, the throughput of the DSP is increased. An existing multiplier may be reconfigured into an adder tree to process the absolute difference results obtained in the first stage. To further increase throughput, multiple DSPs with multiple absolute difference determinators may be operated in parallel.

Abstract: Elimination of dark fixed pattern noise (DFPN) for tethered CMOS sensor-based digital video cameras is supported by supplying and maintaining a host-based dark image cache. Since the camera is tethered to a host computer system such as a PC, it takes advantage of the storage and processing capabilities of the host to manage the cache. By using a dark image cache for updating of the currently applicable dark image for DFPN cancellation processing, operation of the camera shutter for acquiring dark images is dramatically reduced, thereby using less system resources such as power, and increasing the MTBF of the electromechanical devices such as the camera shutter and associated controls. Dark images are obtained at different integration, gain, and temperature operating characteristics of the camera and stored in the cache. The cached dark images are referenced on the host according to a fixed, predetermined dark column of data in video frames generated by the CMOS sensor image array of the camera.