Abstract: An exemplary armature assembly is configured for use with a door control mounted to one of a door or a doorframe. The door control includes a rotatable pinion, and the armature assembly includes an armature, a shoe, and an elastic component. The armature has a first end and an opposite second end, and the first end includes an opening sized and shaped to receive the pinion at a first interface. The shoe is configured for mounting to the other of the door or the doorframe, and the second end of the armature is pivotally connected to the shoe at a second interface. In certain forms, the elastic component coupled with the armature and configured to absorb mechanical shocks at one of the first interface or the second interface. In certain forms, the elastic component is configured to absorb mechanical shocks along the length of the armature.

Abstract: An exemplary armature assembly is configured for use with a door control mounted to one of a door or a doorframe. The door control includes a rotatable pinion, and the armature assembly includes an armature, a shoe, and an elastic component. The armature has a first end and an opposite second end, and the first end includes an opening sized and shaped to receive the pinion at a first interface. The shoe is configured for mounting to the other of the door or the doorframe, and the second end of the armature is pivotally connected to the shoe at a second interface. In certain forms, the elastic component coupled with the armature and configured to absorb mechanical shocks at one of the first interface or the second interface. In certain forms, the elastic component is configured to absorb mechanical shocks along the length of the armature.

Abstract: An exemplary armature assembly is configured for use with a door control mounted to one of a door or a doorframe. The door control includes a rotatable pinion, and the armature assembly includes an armature, a shoe, and an elastic component. The armature has a first end and an opposite second end, and the first end includes an opening sized and shaped to receive the pinion at a first interface. The shoe is configured for mounting to the other of the door or the doorframe, and the second end of the armature is pivotally connected to the shoe at a second interface. In certain forms, the elastic component coupled with the armature and configured to absorb mechanical shocks at one of the first interface or the second interface. In certain forms, the elastic component is configured to absorb mechanical shocks along the length of the armature.

Abstract: An exemplary armature assembly is configured for use with a door control mounted to one of a door or a doorframe. The door control includes a rotatable pinion, and the armature assembly includes an armature, a shoe, and an elastic component. The armature has a first end and an opposite second end, and the first end includes an opening sized and shaped to receive the pinion at a first interface. The shoe is configured for mounting to the other of the door or the doorframe, and the second end of the armature is pivotally connected to the shoe at a second interface. In certain forms, the elastic component coupled with the armature and configured to absorb mechanical shocks at one of the first interface or the second interface. In certain forms, the elastic component is configured to absorb mechanical shocks along the length of the armature.

Abstract: Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.

Abstract: A system and method for semiconductor processing chamber includes a housing that can cover an annular gap of a pedestal well of the semiconductor processing chamber. A cleaning nozzle is removably coupled to a compressed dry air (CDA) supply. The cleaning nozzle can inject the CDA into the pedestal well while the housing can contain a byproduct dust agitated by the injected CDA. The byproduct dust is evacuated by at least one vacuum port that is removably coupled to a vacuum source.

Abstract: Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.

Abstract: Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.

Abstract: A system and method for semiconductor processing chamber includes a housing that can cover an annular gap of a pedestal well of the semiconductor processing chamber. A cleaning nozzle is removably coupled to a compressed dry air (CDA) supply. The cleaning nozzle can inject the CDA into the pedestal well while the housing can contain a byproduct dust agitated by the injected CDA. The byproduct dust is evacuated by at least one vacuum port that is removably coupled to a vacuum source.

Abstract: A communications bridge facilitates communication between an automatic meter reading (AMR) meter and a home area network (HAN) that uses the ZigBee smart energy (SE) protocol. The communications bridge includes a variety of components, including an AMR receiver, a microcontroller, and a ZigBee radio. The AMR receiver reads AMR data, which is not compatible with the ZigBee SE protocol, from the AMR meter. The microcontroller parses the received AMR data and translates it into corresponding ZigBee data. This ZigBee data is transmitted to other devices on the HAN via the ZigBee radio. The translated AMR meter data can then be presented to a consumer in real-time, enabling the consumer to better understand and manage his or her energy usage.

Abstract: A system comprising a storage location to store information representing a timing parameter pertaining to a random access memory device. An integrated circuit device generates a value that is representative of a period of time that elapses between the random access memory device exiting from a power down mode and a time at which the random access memory device is capable of receiving a command. The integrated circuit device generates the value from the information representing the timing parameter pertaining to the random access memory device.

Abstract: A memory device including an array of memory cells, and a register circuit to store a value representative of a period of time to elapse before the memory device is ready to receive a command when recovering from a power down mode is provided in an embodiment. The command specifies an access to the array of memory cells. A delay lock loop circuit synchronizes data transfers using an external clock signal. The delay lock loop circuit reacquires synchronization with the external clock signal during the period of time.

Abstract: A memory module comprises a memory device including a memory array to store data. An interface receives an instruction to exit a power down mode. A register stores a value representative of a period of time to elapse between exiting from the power down mode and a time at which the memory device is capable of receiving a command to access the data. A storage device stores a plurality of parameter information that pertains to the memory device. The value is based on at least a first parameter information of the plurality of parameter information.

Abstract: A memory controller monitors requests from one or more computer subsystems and issues one or more prefetch commands if the memory controller detects that the memory system is idle after a period of activity, or if a prefetch buffer read hit occurs. In some embodiments, results of a prefetching operations are stored in a prefetch buffer configured to provide an automatic aging mechanism, which evicts prefetched data from time to time. The prefetched data in the prefetch buffer is released and sent back to the requester in order with respect to previous memory access requests.

Abstract: A method and apparatus for transferring data across a clock domain boundary is described. In one embodiment, a fixed relationship between a faster clock and a slower clock is maintained in the process of phase alignment to allow great flexibility in allowable combinations of slower clock and faster clock frequencies. In one embodiment, an encoded edge select word is generated once at system initialization and used thereafter to select edges of the faster clock on which to sample data that comes from the clock domain of the slower clock. The value of the encoded edge select word is based, in part, on the fixed relationship between the faster clock and the slower clock.

Abstract: A memory controller monitors requests from one or more computer subsystems and issues one or more prefetch commands if the memory controller detects that the memory system is idle after a period of activity, or if a prefetch buffer read hit occurs. In some embodiments, results of a prefetching operations are stored in a prefetch buffer configured to provide an automatic aging mechanism, which evicts prefetched data from time to time. The prefetched data in the prefetch buffer is released and sent back to the requester in order with respect to previous memory access requests.

Abstract: A system comprising a storage location to store information representing a timing parameter pertaining to a random access memory device. An integrated circuit device generates a value that is representative of a period of time that elapses between the random access memory device exiting from a power down mode and a time at which the random access memory device is capable of receiving a command. The integrated circuit device generates the value from the information representing the timing parameter pertaining to the random access memory device.

Abstract: A memory module comprises a memory device including a memory array to store data. An interface receives an instruction to exit a power down mode. A register stores a value representative of a period of time to elapse between exiting from the power down mode and a time at which the memory device is capable of receiving a command to access the data. A storage device stores a plurality of parameter information that pertains to the memory device. The value is based on at least a first parameter information of the plurality of parameter information.