Abstract: A memory module comprises a random access memory device having a memory array. The random access memory device includes a first register to store a first value that is representative of a number of clock cycles of a clock signal to elapse between latching a column address and an access of data sensed from a row of memory cells in the memory array, wherein a location of the data is based on the column address. A second register stores a second value that is representative of a number of clock cycles of the clock signal to elapse between the access of data from the memory array and outputting the data. A storage device stores a plurality of parameter information that pertains to the random access memory device. The first value and the second value is based on at least a first parameter information of the plurality of parameter information.

Abstract: A method of operation of a memory device and a memory device having registers to store values representing a number of clock cycles to access and output data is provided in embodiments. Data is sensed from an array of memory cells using a plurality of sense amplifiers. A column address that identifies data sensed is latched using the plurality of sense amplifiers. The data is accessed, based on the column address, after a first number of clock cycles of a clock signal have elapsed after latching the column address. The first number of clock cycles is represented by a first value stored in a first register on the memory device. The data is output after a second number of clock cycles have elapsed after accessing the data from the array of memory cells. The second number of clock cycles is represented by a second value stored in a second register on the memory device. A column decoder driving a column select line based on the column address accesses the data.

Abstract: A method of operation of a memory device and system includes receiving a first and second value in embodiments. The first value is representative of a number of clock cycles of a clock signal that elapse between latching a column address and an access of data sensed from a row of memory cells in a memory array. A location of the data is based on the column address. The second value is representative of a number of clock cycles of the clock signal that elapse between the access of data from the memory array and outputting the data. The first and second values are received during an initialization sequence. Information in units of time that represents first and second timing parameters that pertains to the memory device is read from a storage location. The information that represents the first and second timing parameters are then converted from units of time to units of clock cycles to derive the first and second values.

Abstract: Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.

Abstract: A memory device including an array of memory cells, and a register circuit to store a value representative of a period of time to elapse before the memory device is ready to receive a command when recovering from a power down mode is provided in an embodiment. The command specifies an access to the array of memory cells. A delay lock loop circuit synchronizes data transfers using an external clock signal. The delay lock loop circuit reacquires synchronization with the external clock signal during the period of time.

Abstract: Embodiments of the present invention allow a method, device, software and apparatus to adjust a system parameter, such as a page closing time value, in order to enhance a processing device performance. For example, a method includes initializing a page closing time value by a BIOS software component. A processing device, such as a computer, operates responsive to the page closing time value. For example, the computer executes a graphic display software program. An operational value, such as a difference between page hits and page misses, is obtained while executing the software program and compared to a threshold value. The page closing time value is then adjusted responsive to the comparison. In an alternate embodiment of the present invention, an adaptive circuit is included in a memory controller and includes a first counter capable to obtain a number of page hits and a second counter capable to obtain a number of page misses.

Abstract: A method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices coupled to a bus. Determining the response time for a DRAM device comprises writing logic ones to a memory location of the DRAM device using the bus. Subsequently, a read command is issued over the bus, wherein the read command is addressed to the newly-written memory location of the DRAM device. The memory controller then measures the elapsed time between the issuance of the read command and the receipt of the logic ones from the DRAM device, and this elapsed time is the response time of the DRAM device. Following the determination of a response time for each DRAM device, and using the longest response time, a delay is computed for each of the DRAM devices coupled to the bus so that the response time, in clock cycles, of each of the DRAM devices coupled to the bus equals the longest response time.

Abstract: A method and apparatus for transferring data across a clock domain boundary is described. In one embodiment, a fixed relationship between a faster clock and a slower clock is maintained in the process of phase alignment to allow great flexibility in allowable combinations of slower clock and faster clock frequencies. In one embodiment, an encoded edge select word is generated once at system initialization and used thereafter to select edges of the faster clock on which to sample data that comes from the clock domain of the slower clock. The value of the encoded edge select word is based, in part, on the fixed relationship between the faster clock and the slower clock.

Abstract: An apparatus and method for concurrently refreshing first and second rows of memory cells in a dynamic random access memory (DRAM) component that includes a plurality of banks of memory cells organized in rows. A command interface in the DRAM component receives activate requests and precharge requests. A row register in the DRAM component indicates a row in the DRAM component. Logic in the DRAM component activates the row indicated by the row register in response to an activate request and precharges the row in response to a precharge request, the row being in a bank indicated by the activate request and by the precharge request.

Abstract: A memory controller is used in conjunction with a plurality of dynamic memory devices (DRAM's). Each DRAM device has a plurality of adjacent dependent banks of memory cells. The memory controller has a cache. Each entry in the cache corresponds to one bank in one of the dynamic memory devices, and stores information indicating which of the dynamic memory devices the entry corresponds to, whether the bank to which the entry corresponds is open, and which row of the bank was last accessed. Bank status lookup logic is used to access cache entries in response to a memory access request that includes a bank address, a device address and a row address. The bank status lookup logic retrieves an entry, if any, in the cache corresponding to the device address and bank address. It also simultaneously retrieves entries, if any, in the cache for banks physically adjacent to the bank identified by the device address and bank address.

Abstract: A method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices coupled to a bus. Determining the response time for a DRAM device comprises writing logic ones to a memory location of the DRAM device using the bus. Subsequently, a read command is issued over the bus, wherein the read command is addressed to the newly-written memory location of the DRAM device. The memory controller then measures the elapsed time between the issuance of the read command and the receipt of the logic ones from the DRAM device, and this elapsed time is the response time of the DRAM device. Following the determination of a response time for each DRAM device, and using the longest response time, a delay is computed for each of the DRAM devices coupled to the bus so that the response time, in clock cycles, of each of the DRAM devices coupled to the bus equals the longest response time.

Abstract: A memory controller is used in conjunction with a plurality of dynamic memory devices (DRAM's). Each DRAM device has a plurality of adjacent dependent banks of memory cells. The memory controller has a cache. Each entry in the cache corresponds to one bank in one of the dynamic memory devices, and stores information indicating which of the dynamic memory devices the entry corresponds to, whether the bank to which the entry corresponds is open, and which row of the bank was last accessed. Bank status lookup logic is used to access cache entries in response to a memory access request that includes a bank address, a device address and a row address. The bank status lookup logic retrieves an entry, if any, in the cache corresponding to the device address and bank address. It also simultaneously retrieves entries, if any, in the cache for banks physically adjacent to the bank identified by the device address and bank address.

Abstract: A graphics system including a frame buffer having two or more buffers, a graphics processor and system memory. The graphics processor includes rendering logic, display logic and a buffer switch memory that stores an address. The display logic reads the address from the buffer switch memory and retrieves rendered data for display from one of the buffers. The rendering logic retrieves a next display list from the system memory after a continue indication is provided, renders the retrieved display list into another buffer, writes an address corresponding to the other buffer into the buffer switch memory and clears the continue indication. The continue indication may be a separate bit or a continue flag provided within each display list. The rendering logic sequences through the plurality of buffers in this manner to render a plurality of display lists. If only two buffers are provided, then the buffer switch memory includes an arm bit and the rendering logic sets the arm bit after rendering each display list.

Abstract: According to one aspect of the invention, a novel control circuit is coupled to a pin at a circuit node. The circuit node has a particular default condition of one of two logic states. The control circuit stores the default value and subsequently attempts to drive an alternate logic state onto the pin. The circuit then reads the logic state at the pin to determine if there has been a change of logic state registered. If a change has been registered, then the existence of a third condition or fourth condition is indicated, depending upon the default logic state.