Patents by Inventor Bradly G. Frey
Bradly G. Frey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11226902Abstract: A processor core processes a translation load instruction including a protection field specifying a desired access protection to be specified in a translation entry for a memory page. Processing the translation load instruction includes calculating an effective address within the memory page and ensuring that a translation entry containing the desired access protection is stored within at least one translation structure of the data processing system.Type: GrantFiled: September 30, 2019Date of Patent: January 18, 2022Assignee: International Business Machines CorporationInventors: Derek E. Williams, Benjamin Herrenschmidt, Cathy May, Bradly G. Frey
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Patent number: 11119932Abstract: Operation of a multi-slice processor that includes a plurality of execution slices. Operation of such a multi-slice processor includes: determining, by a hypervisor, that consumption of memory controller resources, by a plurality of processing threads, is above a threshold quantity, wherein respective processing threads of the plurality of processing threads control respective prefetch settings; and responsive to determining that the consumption of the memory controller resources is above the threshold quantity, modifying individual memory controller usage of at least one of the plurality of processing threads such that the consumption of the memory controller resources is reduced below the threshold quantity.Type: GrantFiled: March 20, 2019Date of Patent: September 14, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bradly G. Frey, George W. Rohrbaugh, III, Brian W. Thompto
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Publication number: 20210096859Abstract: A processor core processes a translation load instruction including a protection field specifying a desired access protection to be specified in a translation entry for a memory page. Processing the translation load instruction includes calculating an effective address within the memory page and ensuring that a translation entry containing the desired access protection is stored within at least one translation structure of the data processing system.Type: ApplicationFiled: September 30, 2019Publication date: April 1, 2021Inventors: DEREK E. WILLIAMS, BENJAMIN HERRENSCHMIDT, CATHY MAY, BRADLY G. FREY
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Patent number: 10956340Abstract: An apparatus includes a processor and a virtual address transformation unit coupled with the processor. The virtual address transformation unit includes a register. The virtual address transformation unit is configured to receive an indication of a virtual address and read, from the register, a current page size of a plurality of available page sizes. The virtual address transformation unit is also configured to determine a shift amount based, at least in part, on the current page size and perform a bit shift of the virtual address, wherein the virtual address is bit shifted by, at least, the determined shift amount.Type: GrantFiled: February 22, 2019Date of Patent: March 23, 2021Assignee: International Business Machines CorporationInventors: Anthony J. Bybell, Bradly G. Frey, Michael Karl Gschwind
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Patent number: 10817434Abstract: A processor core among the plurality of processor cores initiates invalidation of translation entries buffered in the plurality of processor cores by executing a translation invalidation instruction in an initiating hardware thread. The processor core also executes, in the initiating hardware thread, a synchronization instruction following the translation invalidation instruction in program order that determines completion of invalidation, at all of the plurality of processor cores, of the translation entries specified by the translation invalidation instruction and draining of any memory referent instructions whose target addresses have been translated by reference to the translation entries. A register is updated to a state based on a result of the determination. The processor core branches execution to re-execute the synchronization instruction based on the state of the register indicating that the translation entries are not invalidated at all of the plurality of processor cores.Type: GrantFiled: December 19, 2018Date of Patent: October 27, 2020Assignee: International Business Machines CorporationInventors: Derek E. Williams, Benjamin Herrenschmidt, Cathy May, Bradly G. Frey
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Publication number: 20200201780Abstract: A processor core among the plurality of processor cores initiates invalidation of translation entries buffered in the plurality of processor cores by executing a translation invalidation instruction in an initiating hardware thread. The processor core also executes, in the initiating hardware thread, a synchronization instruction following the translation invalidation instruction in program order that determines completion of invalidation, at all of the plurality of processor cores, of the translation entries specified by the translation invalidation instruction and draining of any memory referent instructions whose target addresses have been translated by reference to the translation entries. A register is updated to a state based on a result of the determination. The processor core branches execution to re-execute the synchronization instruction based on the state of the register indicating that the translation entries are not invalidated at all of the plurality of processor cores.Type: ApplicationFiled: December 19, 2018Publication date: June 25, 2020Inventors: DEREK E. WILLIAMS, BENJAMIN HERRENSCHMIDT, CATHY MAY, BRADLY G. FREY
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Patent number: 10613792Abstract: In a data processing system implementing a weak memory model, a lower level cache receives, from a processor core, a plurality of copy-type requests and a plurality of paste-type requests that together indicate a memory move to be performed. The lower level cache also receives, from the processor core, a barrier request that requests enforcement of ordering of memory access requests prior to the barrier request with respect to memory access requests after the barrier request. In response to the barrier request, the lower level cache enforces a barrier indicated by the barrier request with respect to a final paste-type request ending the memory move but not with respect to other copy-type requests and paste-type requests in the memory move.Type: GrantFiled: August 23, 2018Date of Patent: April 7, 2020Assignee: International Business Machines CorporationInventors: Bradly G. Frey, Guy L. Guthrie, Cathy May, William J Starke, Derek E. Williams
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Patent number: 10387686Abstract: Hardware based isolation for secure execution of virtual machines (VMs). At least one virtual machine is executed via operation of a hypervisor and an ultravisor. A first memory component is configured for access by the hypervisor and the ultravisor, and a second memory component is configured for access by the ultravisor and not by the hypervisor. A first mode of operation is operated, such that the virtual machine is executed using the hypervisor, wherein the first memory component is accessible to the virtual machine and the second memory component is not accessible to the virtual machine. A second mode of operation is operated, such that the virtual machine is executed using the ultravisor, wherein the first memory component and the second memory component are accessible to the virtual machine, thereby executing application code and operating system code using the second memory component without code changes.Type: GrantFiled: July 27, 2017Date of Patent: August 20, 2019Assignee: International Business Machines CorporationInventors: Richard H. Boivie, Bradly G. Frey, William E. Hall, Benjamin Herrenschmidt, Guerney D. H. Hunt, Jentje Leenstra, Paul Mackerras, Cathy May, Albert J. Van Norstrand, Jr.
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Publication number: 20190213133Abstract: Operation of a multi-slice processor that includes a plurality of execution slices. Operation of such a multi-slice processor includes: determining, by a hypervisor, that consumption of memory controller resources, by a plurality of processing threads, is above a threshold quantity, wherein respective processing threads of the plurality of processing threads control respective prefetch settings; and responsive to determining that the consumption of the memory controller resources is above the threshold quantity, modifying individual memory controller usage of at least one of the plurality of processing threads such that the consumption of the memory controller resources is reduced below the threshold quantity.Type: ApplicationFiled: March 20, 2019Publication date: July 11, 2019Inventors: BRADLY G. FREY, GEORGE W. ROHRBAUGH, III, BRIAN W. THOMPTO
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Patent number: 10331566Abstract: Operation of a multi-slice processor that includes a plurality of execution slices. Operation of such a multi-slice processor includes: determining, by a hypervisor, that consumption of memory controller resources, by a plurality of processing threads, is above a threshold quantity, wherein respective processing threads of the plurality of processing threads control respective prefetch settings; and responsive to determining that the consumption of the memory controller resources is above the threshold quantity, modifying individual memory controller usage of at least one of the plurality of processing threads such that the consumption of the memory controller resources is reduced below the threshold quantity.Type: GrantFiled: December 1, 2016Date of Patent: June 25, 2019Assignee: International Business Machines CorporationInventors: Bradly G. Frey, George W. Rohrbaugh, III, Brian W. Thompto
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Publication number: 20190188147Abstract: An apparatus includes a processor and a virtual address transformation unit coupled with the processor. The virtual address transformation unit includes a register. The virtual address transformation unit is configured to receive an indication of a virtual address and read, from the register, a current page size of a plurality of available page sizes. The virtual address transformation unit is also configured to determine a shift amount based, at least in part, on the current page size and perform a bit shift of the virtual address, wherein the virtual address is bit shifted by, at least, the determined shift amount.Type: ApplicationFiled: February 22, 2019Publication date: June 20, 2019Inventors: Anthony J. Bybell, Bradly G. Frey, Michael Karl Gschwind
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Patent number: 10216642Abstract: An apparatus includes a processor and a virtual address transformation unit coupled with the processor. The virtual address transformation unit includes a register. The virtual address transformation unit is configured to receive an indication of a virtual address and read, from the register, a current page size of a plurality of available page sizes. The virtual address transformation unit is also configured to determine a shift amount based, at least in part, on the current page size and perform a bit shift of the virtual address, wherein the virtual address is bit shifted by, at least, the determined shift amount.Type: GrantFiled: March 15, 2013Date of Patent: February 26, 2019Assignee: International Business Machines CorporationInventors: Anthony J. Bybell, Bradly G. Frey, Michael Karl Gschwind
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Publication number: 20190034666Abstract: Hardware based isolation for secure execution of virtual machines (VMs). At least one virtual machine is executed via operation of a hypervisor and an ultravisor. A first memory component is configured for access by the hypervisor and the ultravisor, and a second memory component is configured for access by the ultravisor and not by the hypervisor. A first mode of operation is operated, such that the virtual machine is executed using the hypervisor, wherein the first memory component is accessible to the virtual machine and the second memory component is not accessible to the virtual machine. A second mode of operation is operated, such that the virtual machine is executed using the ultravisor, wherein the first memory component and the second memory component are accessible to the virtual machine, thereby executing application code and operating system code using the second memory component without code changes.Type: ApplicationFiled: July 27, 2017Publication date: January 31, 2019Inventors: Richard H. Boivie, Bradly G. Frey, William E. Hall, Benjamin Herrenschmidt, Guerney D. H. Hunt, Jentje Leenstra, Paul Mackerras, Cathy May, Albert J. Van Norstrand, JR.
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Publication number: 20180373436Abstract: In a data processing system implementing a weak memory model, a lower level cache receives, from a processor core, a plurality of copy-type requests and a plurality of paste-type requests that together indicate a memory move to be performed. The lower level cache also receives, from the processor core, a barrier request that requests enforcement of ordering of memory access requests prior to the barrier request with respect to memory access requests after the barrier request. In response to the barrier request, the lower level cache enforces a barrier indicated by the barrier request with respect to a final paste-type request ending the memory move but not with respect to other copy-type requests and paste-type requests in the memory move.Type: ApplicationFiled: August 23, 2018Publication date: December 27, 2018Inventors: BRADLY G. FREY, GUY L. GUTHRIE, CATHY MAY, WILLIAM J. STARKE, DEREK E. WILLIAMS
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Patent number: 10152322Abstract: A processor core has a store-through upper level cache and a store-in lower level cache. In response to execution of a memory move instruction sequence including a plurality of copy-type instruction and a plurality of paste-type instructions, the processor core transmits a corresponding plurality of copy-type and paste-type requests to the lower level cache, where each copy-type request specifies a source real address and each paste-type request specifies a destination real address. In response to receipt of each copy-type request, the lower level cache copies a respective one of a plurality of data granules from a respective storage location specified by the source real address of that copy-type request into a non-architected buffer. In response to receipt of each paste-type request, the lower level cache writes a respective one of the plurality of data granules from the non-architected buffer to a respective storage location specified by the destination real address of that paste-type request.Type: GrantFiled: August 22, 2016Date of Patent: December 11, 2018Assignee: International Business Machines CorporationInventors: Bradly G. Frey, Sanjeev Ghai, Guy L. Guthrie, Cathy May, William J. Starke, Derek E. Williams
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Patent number: 10067713Abstract: In a data processing system implementing a weak memory model, a lower level cache receives, from a processor core, a plurality of copy-type requests and a plurality of paste-type requests that together indicate a memory move to be performed. The lower level cache also receives, from the processor core, a barrier request that requests enforcement of ordering of memory access requests prior to the barrier request with respect to memory access requests after the barrier request. In response to the barrier request, the lower level cache enforces a barrier indicated by the barrier request with respect to a final paste-type request ending the memory move but not with respect to other copy-type requests and paste-type requests in the memory move.Type: GrantFiled: August 22, 2016Date of Patent: September 4, 2018Assignee: International Business Machines CorporationInventors: Bradly G. Frey, Guy L. Guthrie, Cathy May, William J. Starke, Derek E. Williams
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Publication number: 20180157602Abstract: Operation of a multi-slice processor that includes a plurality of execution slices. Operation of such a multi-slice processor includes: determining, by a hypervisor, that consumption of memory controller resources, by a plurality of processing threads, is above a threshold quantity, wherein respective processing threads of the plurality of processing threads control respective prefetch settings; and responsive to determining that the consumption of the memory controller resources is above the threshold quantity, modifying individual memory controller usage of at least one of the plurality of processing threads such that the consumption of the memory controller resources is reduced below the threshold quantity.Type: ApplicationFiled: December 1, 2016Publication date: June 7, 2018Inventors: BRADLY G. FREY, GEORGE W. ROHRBAUGH, III, BRIAN W. THOMPTO
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Publication number: 20180052606Abstract: In a data processing system implementing a weak memory model, a lower level cache receives, from a processor core, a plurality of copy-type requests and a plurality of paste-type requests that together indicate a memory move to be performed. The lower level cache also receives, from the processor core, a barrier request that requests enforcement of ordering of memory access requests prior to the barrier request with respect to memory access requests after the barrier request. In response to the barrier request, the lower level cache enforces a barrier indicated by the barrier request with respect to a final paste-type request ending the memory move but not with respect to other copy-type requests and paste-type requests in the memory move.Type: ApplicationFiled: August 22, 2016Publication date: February 22, 2018Inventors: BRADLY G. FREY, GUY L. GUTHRIE, CATHY MAY, WILLIAM J. STARKE, DEREK E. WILLIAMS
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Publication number: 20180052687Abstract: A processor core has a store-through upper level cache and a store-in lower level cache. In response to execution of a memory move instruction sequence including a plurality of copy-type instruction and a plurality of paste-type instructions, the processor core transmits a corresponding plurality of copy-type and paste-type requests to the lower level cache, where each copy-type request specifies a source real address and each paste-type request specifies a destination real address. In response to receipt of each copy-type request, the lower level cache copies a respective one of a plurality of data granules from a respective storage location specified by the source real address of that copy-type request into a non-architected buffer. In response to receipt of each paste-type request, the lower level cache writes a respective one of the plurality of data granules from the non-architected buffer to a respective storage location specified by the destination real address of that paste-type request.Type: ApplicationFiled: August 22, 2016Publication date: February 22, 2018Inventors: BRADLY G. FREY, SANJEEV GHAI, GUY L. GUTHRIE, CATHY MAY, WILLIAM J. STARKE, DEREK E. WILLIAMS
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Patent number: 9785557Abstract: In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests, including a translation invalidation request of an initiating hardware thread, are received in a shared queue. The translation invalidation request is broadcast so that it is received and processed by the plurality of processor cores. In response to confirmation of the broadcast, the address translated by the translation entry is stored in a queue. Once the address is stored, the initiating processor core resumes dispatch of instructions within the initiating hardware thread. In response to a request from one of the plurality of processor cores, an effective address translated by a translation entry being invalidated is accessed in the queue. A synchronization request for the address is broadcast to ensure completion of processing of any translation invalidation request for the address.Type: GrantFiled: October 25, 2016Date of Patent: October 10, 2017Assignee: International Business Machines CorporationInventors: Bradly G. Frey, Guy L. Guthrie, Cathy May, Derek E. Williams