Patents by Inventor Bradly G. Frey

Bradly G. Frey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9772945
    Abstract: In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests, including a translation invalidation request of an initiating hardware thread, are received in a shared queue. The translation invalidation request is broadcast so that it is received and processed by the plurality of processor cores. In response to confirmation of the broadcast, the address translated by the translation entry is stored in a queue. Once the address is stored, the initiating processor core resumes dispatch of instructions within the initiating hardware thread. In response to a request from one of the plurality of processor cores, an effective address translated by a translation entry being invalidated is accessed in the queue. A synchronization request for the address is broadcast to ensure completion of processing of any translation invalidation request for the address.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: September 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bradly G. Frey, Guy L. Guthrie, Cathy May, Derek E. Williams
  • Patent number: 9747212
    Abstract: Execution of a store instruction to modify an instruction at a memory location identified by a memory address is requested. A cache controller stores the memory address and the modified data in an associative memory coupled to a data cache and an instruction cache. In addition, the modified data is stored in a second level cache without invalidating the memory location associated with the instruction cache.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 29, 2017
    Assignee: International Business Machines Corporation
    Inventors: Wen-Tzer Thomas Chen, Jr., Robert H. Bell, Jr., Bradly G. Frey
  • Patent number: 9626256
    Abstract: A method for diagnosing an aborted transaction from a plurality of transactions is executed by a processor core with a transactional memory, that stores information corresponding to a plurality of transactions executed by the processor core, and a transaction diagnostic register. The processor core retrieves context summary information from at least one register of the processor core. The processor core stores the context summary information of aborted transactions into the transactional memory or the transaction diagnostic register. The context summary information can be used for diagnosing the aborted transactions.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: April 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Harold W Cain, Bradly G Frey, Hung Q Le, Cathy May
  • Patent number: 9626187
    Abstract: Mechanisms are provided, in a data processing system having a processor and a transactional memory, for executing a transaction in the data processing system. These mechanisms execute a transaction comprising one or more instructions that modify at least a portion of the transactional memory. The transaction is suspended in response to a transaction suspend instruction being executed by the processor. A suspended block of code is executed in a non-transactional manner while the transaction is suspended. A determination is made as to whether an interrupt occurs while the transaction is suspended. In response to an interrupt occurring while the transaction is suspended, a transaction abort operation is delayed until after the transaction suspension is discontinued.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: April 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Harold W. Cain, III, Bradly G. Frey, Benjamin Herrenschmidt, Hung Q. Le, Cathy May, Maged M. Michael, Jose E. Moreira, Priya A. Nagpurkar, Naresh Nayar, Randal C. Swanberg
  • Patent number: 9619345
    Abstract: A processor core includes a transactional memory that stores information corresponding to a plurality of transactions executed by the processor core, and a transaction diagnostic register. The processor core retrieves context summary information from at least one register of the processor core. The processor core stores the context summary information of aborted transactions into the transactional memory or the transaction diagnostic register. The context summary information can be used for diagnosing the aborted transactions.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: April 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: Harold W Cain, Bradly G Frey, Hung Q Le, Cathy May
  • Patent number: 9600419
    Abstract: An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration, and the use of a particular translation structure format in translating an address is selectable.
    Type: Grant
    Filed: October 8, 2012
    Date of Patent: March 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Bybell, Bradly G. Frey, Michael K. Gschwind
  • Patent number: 9575825
    Abstract: A processor core of a data processing system receives a push instruction of a sending thread that requests that a message payload identified by at least one operand of the push instruction be pushed to a mailbox of a receiving thread. In response to receiving the push instruction, the processor core executes the push instruction of the sending thread. In response to executing the push instruction, the processor core initiates transmission of the message payload to the mailbox of the receiving thread. In one embodiment, the processor core initiates transmission of the message payload by transmitting a co-processor request to a switch of the data processing system via an interconnect fabric.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: February 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Lakshminarayana B. Arimilli, Bernard C. Drerup, Bradly G. Frey, Guy L. Guthrie, John D. Irish, William J. Starke, Jeffrey A. Stuecheli
  • Patent number: 9569293
    Abstract: A processor core of a data processing system receives a push instruction of a sending thread that requests that a message payload identified by at least one operand of the push instruction be pushed to a mailbox of a receiving thread. In response to receiving the push instruction, the processor core executes the push instruction of the sending thread. In response to executing the push instruction, the processor core initiates transmission of the message payload to the mailbox of the receiving thread. In one embodiment, the processor core initiates transmission of the message payload by transmitting a co-processor request to a switch of the data processing system via an interconnect fabric.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: February 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Lakshminarayana B. Arimilli, Bernard C. Drerup, Bradly G. Frey, Guy L. Guthrie, John D. Irish, William J. Starke, Jeffrey A. Stuecheli
  • Patent number: 9430166
    Abstract: In a processor, an instruction sequence including, in order, a load-and-reserve instruction specifying a read access to a target memory block, an instruction delimiting transactional memory access instructions belonging to a memory transaction, and a store-conditional instruction specifying a conditional write access to the target memory block is detected. In response to detecting the instruction sequence, the processor causes the conditional write access to the target memory block to fail.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: August 30, 2016
    Assignee: International Business Machines Corporation
    Inventors: Bradly G. Frey, Guy L. Guthrie, Cathy May, Derek E. Williams
  • Patent number: 9396115
    Abstract: In a multiprocessor data processing system having a distributed shared memory system, a memory transaction that is a rewind-only transaction (ROT) and that includes one or more transactional memory access instructions and a transactional abort instruction is executed. In response to execution of the one or more transactional memory access instructions, one or more memory accesses to the distributed shared memory system indicated by the one or more transactional memory access instructions are performed. In response to execution of the transactional abort instruction, execution results of the one or more transaction memory access instructions are discarded and control is passed to a fail handler.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: July 19, 2016
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Blainey, Bradly G. Frey, Guy L. Guthrie, Cathy May, Derek E. Williams
  • Publication number: 20160179591
    Abstract: A processor core of a data processing system receives a push instruction of a sending thread that requests that a message payload identified by at least one operand of the push instruction be pushed to a mailbox of a receiving thread. In response to receiving the push instruction, the processor core executes the push instruction of the sending thread. In response to executing the push instruction, the processor core initiates transmission of the message payload to the mailbox of the receiving thread. In one embodiment, the processor core initiates transmission of the message payload by transmitting a co-processor request to a switch of the data processing system via an interconnect fabric.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: LAKSHMINARAYANA B. ARIMILLI, BERNARD C. DRERUP, BRADLY G. FREY, GUY L. GUTHRIE, JOHN D. IRISH, WILLIAM J. STARKE, JEFFREY A. STUECHELI
  • Publication number: 20160179593
    Abstract: A processor core of a data processing system receives a push instruction of a sending thread that requests that a message payload identified by at least one operand of the push instruction be pushed to a mailbox of a receiving thread. In response to receiving the push instruction, the processor core executes the push instruction of the sending thread. In response to executing the push instruction, the processor core initiates transmission of the message payload to the mailbox of the receiving thread. In one embodiment, the processor core initiates transmission of the message payload by transmitting a co-processor request to a switch of the data processing system via an interconnect fabric.
    Type: Application
    Filed: June 8, 2015
    Publication date: June 23, 2016
    Inventors: LAKSHMINARAYANA B. ARIMILLI, BERNARD C. DRERUP, BRADLY G. FREY, GUY L. GUTHRIE, JOHN D. IRISH, WILLIAM J. STARKE, JEFFREY A. STUECHELI
  • Patent number: 9367263
    Abstract: A processing unit of a data processing system having a shared memory system executes a memory transaction including a transactional store instruction that causes a processing unit of the data processing system to make a conditional update to a target memory block of the shared memory system conditioned on successful commitment of the memory transaction. The memory transaction further includes a transaction check instruction. In response to executing the transaction check instruction, the processing unit determines, prior to conclusion of the memory transaction, whether the target memory block of the shared memory system was modified after the conditional update caused by execution of the transactional store instruction. In response to determining that the target memory block has been modified, a condition register within the processing unit is set to indicate a conflict for the memory transaction.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: June 14, 2016
    Assignee: International Business Machines Corporation
    Inventors: Bradly G. Frey, Guy L. Guthrie, Cathy May, Derek E. Williams
  • Patent number: 9367264
    Abstract: A processing unit of a data processing system having a shared memory system executes a memory transaction including a transactional store instruction that causes a processing unit of the data processing system to make a conditional update to a target memory block of the shared memory system conditioned on successful commitment of the memory transaction. The memory transaction further includes a transaction check instruction. In response to executing the transaction check instruction, the processing unit determines, prior to conclusion of the memory transaction, whether the target memory block of the shared memory system was modified after the conditional update caused by execution of the transactional store instruction. In response to determining that the target memory block has been modified, a condition register within the processing unit is set to indicate a conflict for the memory transaction.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: June 14, 2016
    Assignee: International Business Machines Corporation
    Inventors: Bradly G. Frey, Guy L. Guthrie, Cathy May, Derek E. Williams
  • Patent number: 9348763
    Abstract: An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration. This facilitates provision of guest access in virtualized operating systems, and/or the mixing of translation formats to better match the data access patterns being translated.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: May 24, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Bybell, David D. Dukro, Bradly G. Frey, Michael K. Gschwind
  • Patent number: 9342454
    Abstract: In a multiprocessor data processing system having a distributed shared memory system, first and second nested memory transactions are executed, where the first memory transaction is a rewind-only transaction (ROT) and the second memory transaction is a non-ROT memory transaction. The first memory transaction has a transaction body including the second memory transaction and an additional plurality of transactional memory access instructions. In response to execution of the transactional memory access instructions, memory accesses are performed to the distributed shared memory system. Conflicts between memory accesses not within the first memory transaction and at least a load footprint of any of the transactional memory access instructions preceding the second memory transaction are not tracked.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: May 17, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bradly G. Frey, Guy L. Guthrie, Cathy May, Derek E. Williams
  • Patent number: 9330023
    Abstract: For a current context in control of a processor requesting access to a particular address, a translation lookaside buffer (TLB) controller specifies a virtual address with a logical partition identifier value indicating a privilege setting of the current context, a process identifier value indicating whether the address is within shared address space, and an effective address comprising at least a portion of the particular address.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: May 3, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Bybell, Bradly G. Frey, Michael K. Gschwind, Benjamin Herrenschmidt, Paul Mackerras
  • Patent number: 9323692
    Abstract: In response to a current context, with a particular process currently in control of a processor requesting access to a shared address space, a translation lookaside buffer (TLB) controller sets a process identifier field in a virtual address to be looked up in a TLB to a clamped value different from an identifier for the process, wherein the virtual address comprises at least the process identifier field and an effective address field set to an address in the requested shared address space. In response to the TLB controller comparing the virtual address for the current context to a particular entry of at least one entry within the TLB comprising the at least one entry stored for a previous translation of a previous virtual address, the TLB controller only indicates a match between the process identifier field and a translation process identifier field within the particular entry of the TLB if the translation process identifier field is also set to the clamped value.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: April 26, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Bybell, Bradly G. Frey, Michael K. Gschwind, Benjamin Herrenschmidt, Paul MacKerras
  • Patent number: 9317443
    Abstract: For a current context in control of a processor requesting access to a particular address, a translation lookaside buffer (TLB) controller specifies a virtual address with a logical partition identifier value indicating a privilege setting of the current context, a process identifier value indicating whether the address is within shared address space, and an effective address comprising at least a portion of the particular address.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: April 19, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Bybell, Bradly G. Frey, Michael K. Gschwind, Benjamin Herrenschmidt, Paul Mackerras
  • Patent number: 9311249
    Abstract: In response to a current context, with a particular process currently in control of a processor requesting access to a shared address space, a translation lookaside buffer (TLB) controller sets a process identifier field in a virtual address to be looked up in a TLB to a clamped value different from an identifier for the process, wherein the virtual address comprises at least the process identifier field and an effective address field set to an address in the requested shared address space. In response to the TLB controller comparing the virtual address for the current context to a particular entry of at least one entry within the TLB comprising the at least one entry stored for a previous translation of a previous virtual address, the TLB controller only indicates a match between the process identifier field and a translation process identifier field within the particular entry of the TLB if the translation process identifier field is also set to the clamped value.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: April 12, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Bybell, Bradly G. Frey, Michael K. Gschwind, Benjamin Herrenschmidt, Paul Mackerras