Abstract: An apparatus comprising a local oscillator (LO) for driving a mixer, the LO being configured to oscillate at an oscillation frequency, and generate a first set of LO signals, wherein each of the first set of LO signals has a LO signal frequency equal to a first multiplication factor m multiplied by the oscillation frequency, the first multiplication factor m, being an integer greater than or equal to two, and each of the first set of LO signals is separated by adjacent LO signals by a phase difference equal to 360° divided by a first variable n, the first variable n being an integer that is greater than or equal to two.

Abstract: A temperature sensor and method of temperature sensing is described. A first reference current is provided to a dual-slope ADC during a first slope time duration of a dual-slope ADC conversion cycle. A second reference current is provided to the dual-slope ADC during a second slope time duration of the dual-slope ADC conversion cycle. A digital codeword corresponding to a ratio of the first and second reference currents is then output by the dual-slope ADC. The first and second reference current ratio is related to the temperature.

Abstract: A frequency reference generator includes (i) an integrated frequency source having drive circuitry that drives a resonant (e.g., non-trimmable LC) tank to generate an oscillator signal, (ii) at least one temperature sensor that generates at least one measured temperature signal, and (iii) a frequency-adjustment circuit that adjusts the oscillator signal frequency to generate the frequency reference based on the measured temperature signal and a (e.g., sample-specific) mapping from temperature to a corresponding frequency-adjustment parameter (e.g., a divisor value for a fractional frequency divider). In some embodiments, a Colpitts oscillator generates the oscillator signal based on the measured temperature signal, where the Colpitts oscillator has voltage/temperature-compensation circuitry that compensates for variations in power supply voltage and operating temperature. Such frequency reference generators achieve substantial PVT insensitivity with as little as a single 1T-trim or even no trim at all.

Abstract: Systems and methods for analog finite impulse response (FIR) filters are provided. In certain embodiments, a receiver includes a cascade of a mixer, an analog FIR filter, and an analog-to-digital converter (ADC). By including the analog FIR filter along the signal path between the mixer and the ADC, design constraints of the ADC are relaxed. For example, the ADC can operate with relaxed specifications with respect to resolution and/or dynamic range when the analog FIR filter is included. The analog FIR filter can include a controllable transconductance circuit that delivers an integration current to a capacitor over an integration period, with the analog FIR filter's coefficients used to change the transconductance setting of the controllable transconductance circuit to different values over the integration period.

Abstract: Systems and methods for analog finite impulse response (FIR) filters are provided. In certain embodiments, a receiver includes a cascade of a mixer, an analog FIR filter, and an analog-to-digital converter (ADC). By including the analog FIR filter along the signal path between the mixer and the ADC, design constraints of the ADC are relaxed. For example, the ADC can operate with relaxed specifications with respect to resolution and/or dynamic range when the analog FIR filter is included. The analog FIR filter can include a controllable transconductance circuit that delivers an integration current to a capacitor over an integration period, with the analog FIR filter's coefficients used to change the transconductance setting of the controllable transconductance circuit to different values over the integration period.

Abstract: Clock systems with phase noise compensation are provided herein. In certain implementations, a clock system includes a phase noise detector for detecting a phase noise of a clock signal, and an adjustable delay circuit for generating an adjusted clock signal based on delaying the clock signal with a controllable delay. Additionally, the phase noise detector generates an error signal indicated the phase noise of the clock signal, and controls the delay of the adjustable delay circuit with the error signal over time to thereby compensate the clock signal for phase noise. Thus, the adjusted clock signal has reduced phase noise compared to the clock signal.

Abstract: Clock systems with phase noise compensation are provided herein. In certain implementations, a clock system includes a phase noise detector for detecting a phase noise of a clock signal, and an adjustable delay circuit for generating an adjusted clock signal based on delaying the clock signal with a controllable delay. Additionally, the phase noise detector generates an error signal indicated the phase noise of the clock signal, and controls the delay of the adjustable delay circuit with the error signal over time to thereby compensate the clock signal for phase noise. Thus, the adjusted clock signal has reduced phase noise compared to the clock signal.

Abstract: Provided is a wireless communication receiver including an antenna for receiving an RF signal; a first mixer, coupled to the antenna, for performing frequency conversion on the RF signal from the antenna by mixing the RF signal with a local oscillator signal to provide a first intermediate frequency (IF) signal; and a first filter, coupled to the first mixer, configured to pass a predetermined band of frequencies of the first IF signal and to generate a first channel signal. The first filter includes a negative feedback loop coupled to the first mixer for performing negative feedback loop control on the first IF signal; and a positive capacitive feedback loop coupled to the first mixer for performing positive capacitive feedback loop control on the first IF signal, the negative feedback loop and the positive capacitive feedback loop being coupled in parallel.

Abstract: Provided is a wireless communication receiver including an antenna for receiving an RF signal; a first mixer, coupled to the antenna, for performing frequency conversion on the RF signal from the antenna by mixing the RF signal with a local oscillator signal to provide a first intermediate frequency (IF) signal; and a first filter, coupled to the first mixer, configured to pass a predetermined band of frequencies of the first IF signal and to generate a first channel signal. The first filter includes a negative feedback loop coupled to the first mixer for performing negative feedback loop control on the first IF signal; and a positive capacitive feedback loop coupled to the first mixer for performing positive capacitive feedback loop control on the first IF signal, the negative feedback loop and the positive capacitive feedback loop being coupled in parallel.

Abstract: A wireless receiver with high linearity, having an out-band signal bypass filter, a mixer, and a baseband circuit. The out-band signal bypass filter has a first terminal and a second terminal respectively receiving a positive differential signal and a negative differential signal from a former-stage circuit, and the out-band signal bypass filter provides an out-band signal bypass path from the first terminal to the second terminal. The mixer receives a filtered signal from the out-band signal bypass filter. The baseband circuit is coupled to the mixer for generation of an in-phase signal and a quadrature phase signal.

Abstract: Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transistor and first P-channel transistor are coupled to an output conductor. A first degeneration resistor is coupled between a source of the first P-channel transistor and a first supply voltage and a second degeneration resistor is coupled between a source of the first N-channel transistor and a second supply voltage. A first low impedance bypass circuit is coupled between the sources of the first P-channel transistor and the first N-channel transistor.

Abstract: A Silicon On Insulator current source array includes input control for receiving a control voltage, a first reference input for receiving a first reference voltage, and a second reference input for receiving a second reference voltage. A chain of several Silicon On Insulator MOS transistors, of the same type, have control electrodes all connected to the input control, first conduction electrodes are all connected to the first reference input, and second conduction electrodes are respectively connected to the second reference input through several load circuits respectively configured to be traversed by several currents when the several transistors are ON upon application of the control voltage on the input control. An input bias is coupled to a semiconductor well located below an insulating buried layer located below the chain of transistors for receiving a biasing voltage difference.

Abstract: A wireless receiver with high linearity, having an out-band signal bypass filter, a mixer, and a baseband circuit. The out-band signal bypass filter has a first terminal and a second terminal respectively receiving a positive differential signal and a negative differential signal from a former-stage circuit, and the out-band signal bypass filter provides an out-band signal bypass path from the first terminal to the second terminal. The mixer receives a filtered signal from the out-band signal bypass filter. The baseband circuit is coupled to the mixer for generation of an in-phase signal and a quadrature phase signal.

Abstract: Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transistor and first P-channel transistor are coupled to an output conductor. A first degeneration resistor is coupled between a source of the first P-channel transistor and a first supply voltage and a second degeneration resistor is coupled between a source of the first N-channel transistor and a second supply voltage. A first low impedance bypass circuit is coupled between the sources of the first P-channel transistor and the first N-channel transistor.

Abstract: A low power frequency synthesizer circuit for a radio transceiver, the synthesizer circuit comprising: a digital controlled oscillator configured to generate an output signal (Fo) having a frequency controlled by an input digital control word (DCW); a feedback loop connected between an output and an input of the digital controlled oscillator, the feedback loop configured to provide the digital control word to the input of the digital controlled oscillator from an error derived from an input frequency control word (FCW) and the output signal; and a duty cycle module connected to the digital controlled oscillator and the feedback loop, the duty cycle module configured to generate a plurality of control signals to periodically enable and disable the digital controlled oscillator for a set fraction of clock cycles of an input reference clock signal (RefClock).

Abstract: A Silicon On Insulator current source array includes input control for receiving a control voltage, a first reference input for receiving a first reference voltage, and a second reference input for receiving a second reference voltage. A chain of several Silicon On Insulator MOS transistors, of the same type, have control electrodes all connected to the input control, first conduction electrodes are all connected to the first reference input, and second conduction electrodes are respectively connected to the second reference input through several load circuits respectively configured to be traversed by several currents when the several transistors are ON upon application of the control voltage on the input control. An input bias is coupled to a semiconductor well located below an insulating buried layer located below the chain of transistors for receiving a biasing voltage difference.

Abstract: A polyphase harmonic rejection mixer, comprising a plurality of stages following each other; wherein a first stage is arranged to perform at least frequency conversion; and a second stage is arranged to perform at least selective weighting and combining; wherein at least two of the plurality of stages are arranged to perform at least combining. In an embodiment, the first stage (28) comprises three single-ended gain blocks (10, 12, 14), arranged to perform selective weighting, frequency conversion and combining; and a second stage (30) following the first stage (28) and arranged to perform selective weighting and combining. The second stage (30) may reduce the number of phases output by the first stage (28) and may output (32) a complex differential down converted signal. The mixer may be directly interfaced to an antenna of an LNA-less receiver without weighting in the first stage. The mixer may be included in a software-defined radio.

Abstract: A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.

Abstract: Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of one or more sampling control signals, power consumption by the reference signal buffer and spurious output signals from the sampling PLL being controlled can be reduced.

Abstract: Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.