Abstract: Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.

Abstract: A low power frequency synthesiser circuit (30) for a radio transceiver, the synthesiser circuit comprising: a digital controlled oscillator (33) configured to generate an output signal (F0) having a frequency controlled by an input digital control word (DCW); a feedback loop (35-38) connected between an output and an input of the digital controlled oscillator, the feedback loop configured to provide the digital control word to the input of the digital controlled oscillator from an error derived from an input frequency control word (FCW) and the output signal; and a duty cycle module (32) connected to the digital controlled oscillator and the feedback loop, the duty cycle module configured to generate a plurality of control signals to periodically enable and disable the digital controlled oscillator for a set fraction of clock cycles of an input reference clock signal (RefClock).

Abstract: A polyphase harmonic rejection mixer, comprising a plurality of stages following each other; wherein a first stage is arranged to perform at least frequency conversion; and a second stage is arranged to perform at least selective weighting and combining; wherein at least two of the plurality of stages are arranged to perform at least combining. In an embodiment, the first stage (28) comprises three single-ended gain blocks (10, 12, 14), arranged to perform selective weighting, frequency conversion and combining; and a second stage (30) following the first stage (28) and arranged to perform selective weighting and combining. The second stage (30) may reduce the number of phases output by the first stage (28) and may output (32) a complex differential down converted signal. The mixer may be directly interfaced to an antenna of an LNA-less receiver without weighting in the first stage. The mixer may be included in a software-defined radio.

Abstract: Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal.

Abstract: A frequency divider comprising, a first latch circuit and a second latch circuit, the second latch circuit being crossed-coupled to the first latch circuit. Each latch comprises a respective sense amplifier coupled to a respective latch. The sense amplifiers comprise a first clock input for receiving a first clock signal. The latches comprise a second clock input for receiving a second clock signal having a second frequency, the second frequency being substantially double the first frequency.

Abstract: A frequency divider includes a first latch and a second latch. The first latch is configured to receive a clock signal. The first latch is cross-coupled to the second latch. The second latch includes a circuit configured as a low-pass filter. The second latch further includes a differential pair of transistors. Each of the transistors include a drain, a source and a gate. The gates of the at least two transistors configured to receive a signal generated by the first latch. Additionally, the gates of the at least two other transistors are coupled to a control signal for determining a low-pass characteristic of the second latch.

Abstract: The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a feedback signal derived from an output oscillation signal are divided by a predetermined rate to thereby reduce the frequency at a phase detection means (1) of the PLL circuit. The dividing step is inhibited in response to a detection of a phase-locked-state of the PLL circuit. Thus, after phase-lock has been achieved, extra reference dividers (6) added to decrease the comparison frequency are removed from the loop to thereby enable increase in the loop bandwidths and decrease in the dividing ratio within the loop.

Abstract: A frequency divider comprising, a first latch circuit (10) and a second latch circuit (10), the second latch circuit (10?) being crossed-coupled to the first latch circuit (10). Each latch (10; 10?) comprises a respective sense amplifier coupled to a respective latch (11). The sense amplifiers comprise a first clock input for receiving a first clock signal (f, f) and 5 respective complementary first clock signal having a first frequency. The latches (11) comprise a second clock input (2f; 2f) for receiving a second clock signal and respective complementary second clock signal having a second frequency, the second frequency being substantially double the first frequency.

Abstract: A phase locked loop comprising a phase detector (100) for determining a phase difference between a reference signal (Ref) and mutually phase shifted signals (I, Q) to generate frequency control signals (U, D), the phase detector (100) comprising: means (10) for obtaining a first one of said frequency control signals (U, D) by binary multiplication of the reference signal (Ref) and one of the relative phase shifted signals (I, Q); and means (20) for obtaining a second one of said frequency control signals (U, D) by binary multiplication of the relative phase shifted signals (I, Q).

Abstract: A phase locked loop comprising a phase detector (100) for determining a phase difference between a reference signal (Ref) and mutually phase shifted signals (I, Q) to generate frequency control signals (U, D), the phase detector (100) comprising: means (10) for obtaining a first one of said frequency control signals (U, D) by binary multiplication of the reference signal (Ref) and one of the relative phase shifted signals (I, Q); and means (20) for obtaining a second one of said frequency control signals (U, D) by binary multiplication of the relative phase shifted signals (I, Q).

Abstract: The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a feedback signal derived from an output oscillation signal are divided by a predetermined rate to thereby reduce the frequency at a phase detection means (1) of the PLL circuit. The dividing step is inhibited in response to a detection of a phase-locked-state of the PLL circuit. Thus, after phase-lock has been achieved, extra reference dividers (6) added to decrease the comparison frequency are removed from the loop to thereby enable increase in the loop bandwidths and decrease in the dividing ratio within the loop.

Abstract: A two-wire interface for a digital microphone circuit includes a power line and a ground line. The interface utilizes the ground line as a “voltage active line” to transmit both clock and data signals between the digital microphone circuit and a receiving circuit. The digital microphone circuit detects the clock signal on the voltage active line and uses the detected clock signal to operate an ADC to provide digital data. The digital data is used to selectively drive current back to the receiving circuit over the voltage active line. The receiving circuit detects the transmitted data by monitoring the voltage associated with a line termination. The impedance associated with the line termination is switched by the receiver circuit to modulate the clock signal on the voltage active line.

Abstract: A line driver comprising a first transistor (M1), a first amplifier (A1) and a reference resistor (10) for converting an input voltage (Vin) to a first current (i1) through the first transistor (M1). A second current i2=n*i1 flows through a second transistor (M2) which forms a 1:n current mirror with the first transistor (M1). The current i2 flows to a load (6), if so required via a transmission line (TL). The impedance of the load (6) is equal to the characteristic impedance RL of the transmission line (TL). Thus the impedance seen by the line driver is equal to RL. A second transconductance amplifier (A2) counteracts reflected signals in the output signal (Vout) caused by mismatch between the output impedance of the current mirror (M1, M2) and the impedance seen by the line driver.

Abstract: A line driver comprising a first transistor (M1), a first operational transconductance amplifier (A1) and a reference resistor (10) for converting an input voltage (Vin) to a first current (i1) through the first transistor (M1). A second current i2=n*i1 flows through a second transistor (M2) which forms a 1:n current mirror with the first transistor (M1). The current i2 flows to a load (6), if so required via a transmission line (TL). The impedance of the load (6) is equal to the characteristic impedance RL of the transmission line (TL). Thus, the impedance seen by the line driver is equal to RL. A second operational transconductance amplifier (A2) counteracts reflected signals in the output signal (Vout) caused by mismatch between the output impedance of the current mirror (M1, M2) and the impedance seen by the line driver.

Abstract: A differential pair with input transistors and provided with a variable degeneration resistor. The degeneration resistor comprises a series arrangement of two branches of coupled resistors which are shunted in mutually corresponding points by respective control transistors whose gates are interconnected. The differential pair further comprises a control loop comprising two current mirrors a bias resistor and a current source for providing a control signal to the gates of the control transistors. The control loop does not influence the DC bias of the differential pair.

Abstract: A folding stage for a folding analog-to-digital converter includes a plurality of consecutive reference terminals providing ascending different reference voltages, a first summing node, a second summing node and a first output node. A plurality of differentially coupled transistor pairs wherein each of the pairs has a first transistor having a main current path and a control electrode which is coupled to an input terminal (IT) for receiving an input voltage to be folded and a second transistor having a main current path and a control electrode which is coupled to a respective one of the consecutive reference terminals. The main current path of the first transistor of the consecutive transistor pairs is coupled alternately to the first summing node and the second summing node, and the main current path of the associated second transistor is coupled alternately to the second summing node and the first summing node.

Abstract: A folding stage for a folding analog-to-digital converter comprising a plurality of consecutive reference terminals for providing ascending different reference voltages; a first summing node, a second summing node and a first output node. A plurality of differentially coupled transistor pairs with each one of the pairs comprising a first transistor having a main current path and a control electrode which is coupled to an input terminal for receiving an input voltage to be folded and a second transistor having a main current path and a control electrode which is coupled to a respective one of the consecutive reference terminals. The main current path of the first transistor of consecutive transistor pairs is coupled alternately to the first summing node and the second summing node, and the main current path of the associated second transistor is coupled alternately to the second summing node and the first summing node.

Abstract: A line driver comprising: an input terminal for receiving an input signal, an output terminal for connecting a load, a first and a second transconductance-controlled transconductor having substantially equal transconductances, each transconductor having a non-inverting input, an inverting input, an output and a common control input for controlling the transconductance, the non-inverting inputs of the first and second transconductors being coupled to the input terminal, the outputs of the first and second transconductors being coupled to the output terminal, the inverting input of the first transconductor being coupled to a point of reference potential, the inverting input of the second transconductor being coupled to the output terminal, and an amplifier having a non-inverting input, an inverting input and an output coupled to, respectively, the input terminal, the output terminal and the common control input of the first and the second transconductors.

Abstract: A single-to-differential converter for generating two balanced output signals from one single-ended input signal includes first (3) and second (6) output terminals for providing the balanced output signal, a first transistor (M1) having a control electrode coupled to an input terminal (4) for receiving the input signal, a first main electrode coupled to a supply voltage terminal (1) for receiving a supply voltage and a second main electrode coupled to the first output terminal (3). A second transistor (M2) is provided having a control electrode coupled to a bias voltage terminal (5), a first main electrode coupled to the control electrode of the first transistor (M1) and a second main electrode connected to the second output terminal (6). A diode-connected third transistor (M3) is provided having its main current path coupled to the first output terminal (3), and a diode-connected fourth transistor (M4) is provided having its main current path connected to the second output terminal (6).

Abstract: An electrically controllable oscillator circuit (30) comprises two balanced transconductance circuits (G1, G2), each including transistor pairs arranged as inverters (Inv14) and as resistors (Inv5-6). The oscillation frequency (f) and the quality factor (Q) of the oscillator circuit (30) are controlled by means of a single control signal provided by a combined control circuit (Inv7, Dif, IM1, IM2). The current mirror circuit (IM1, IM2) and a differential pair (Dif) derived the control signal for adjusting the quality factor (Q) from a resistor-connected further transistor pair (Inv7) connected to the control signal for adjusting the frequency (f). The quality factor of an electrically controllable filter arangement including similar transconductance circuits (G-3-9) is adjusted by means of the control signal generated by the control circuit via a buffer circuit (B) and a low-pass circuit (C3).