Patents by Inventor Brendan BARRY
Brendan BARRY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170293346Abstract: A vector processor is disclosed including a variety of variable-length instructions. Computer-implemented methods are disclosed for efficiently carrying out a variety of operations in a time-conscious, memory-efficient, and power-efficient manner. Methods for more efficiently managing a buffer by controlling the threshold based on the length of delay line instructions are disclosed. Methods for disposing multi-type and multi-size operations in hardware are disclosed. Methods for condensing look-up tables are disclosed. Methods for in-line alteration of variables are disclosed.Type: ApplicationFiled: December 16, 2016Publication date: October 12, 2017Inventors: Brendan BARRY, Fergal CONNOR, Martin O'RIORDAN, David MOLONEY, Sean POWER
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Publication number: 20170287447Abstract: Systems and methods are provided for rendering of a dual eye-specific display. The system tracks the user's eye movements and/or positions, in some implementations, based on electroencephalography (EEG) of the user, to correctly label the central (foveal) and peripheral (extra-foveal) areas of the display. Foveal data is fully rendered while extra-foveal data is reduced in resolution and, in some implementations, shared between the two displays.Type: ApplicationFiled: April 1, 2016Publication date: October 5, 2017Applicant: Linear Algebra Technologies LimitedInventors: Brendan BARRY, David MOLONEY
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Patent number: 9727113Abstract: The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices.Type: GrantFiled: August 12, 2014Date of Patent: August 8, 2017Assignee: LINEAR ALGEBRA TECHNOLOGIES LIMITEDInventors: Brendan Barry, Richard Richmond, Fergal Connor, David Moloney
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Publication number: 20170116718Abstract: One of the challenges in bringing computational imaging to a mass market is that computational imaging is inherently computationally expensive. The computational challenges associated with computational imaging are apparent with the computation of a histogram of gradient descriptors. Oftentimes, generating a histogram of gradient descriptors involves computing gradients of an image, binning the gradients according to their orientation, and, optionally, normalizing the bins using a non-linear function. Because each of these operations is expensive, the histogram of gradient descriptor computations is generally computationally expensive and is difficult to implement in a power efficient manner for mobile applications. The present application discloses a computing device that can provide a low-power, highly capable computing platform for computing a histogram of gradient descriptors.Type: ApplicationFiled: October 31, 2016Publication date: April 27, 2017Inventors: Richard RICHMOND, Cormac BRICK, Brendan BARRY, David MOLONEY
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Patent number: 9483706Abstract: One of the challenges in bringing computational imaging to a mass market is that computational imaging is inherently computationally expensive. The computational challenges associated with computational imaging are apparent with the computation of a histogram of gradient descriptors. Oftentimes, generating a histogram of gradient descriptors involves computing gradients of an image, binning the gradients according to their orientation, and, optionally, normalizing the bins using a non-linear function. Because each of these operations is expensive, the histogram of gradient descriptor computations is generally computationally expensive and is difficult to implement in a power efficient manner for mobile applications. The present application discloses a computing device that can provide a low-power, highly capable computing platform for computing a histogram of gradient descriptors.Type: GrantFiled: January 8, 2015Date of Patent: November 1, 2016Assignee: Linear Algebra Technologies LimitedInventors: Richard Richmond, Cormac Brick, Brendan Barry, David Moloney
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Publication number: 20160203384Abstract: One of the challenges in bringing computational imaging to a mass market is that computational imaging is inherently computationally expensive. The computational challenges associated with computational imaging are apparent with the computation of a histogram of gradient descriptors. Oftentimes, generating a histogram of gradient descriptors involves computing gradients of an image, binning the gradients according to their orientation, and, optionally, normalizing the bins using a non-linear function. Because each of these operations is expensive, the histogram of gradient descriptor computations is generally computationally expensive and is difficult to implement in a power efficient manner for mobile applications. The present application discloses a computing device that can provide a low-power, highly capable computing platform for computing a histogram of gradient descriptors.Type: ApplicationFiled: January 8, 2015Publication date: July 14, 2016Inventors: Richard RICHMOND, Cormac BRICK, Brendan BARRY, David MOLONEY
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Publication number: 20150366214Abstract: This invention relates to regenerable antimicrobial coatings with long-lasting efficacy for use in medical applications including implants, medical instruments or devices, and hospital equipment. The same coatings would also have broad utility in the consumer, industrial, and institutional markets. The coating technology is based on sequestration of hydrogen peroxide (HP) by zinc oxide binders incorporated into the coatings.Type: ApplicationFiled: June 17, 2015Publication date: December 24, 2015Applicant: Quick-Med Technologies, Inc.Inventors: William Toreki, Rustom Sam Kanga, Bernard Christopher Crampsie, Brendan Barry Wynn
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Patent number: 9196017Abstract: The disclosed embodiments include an apparatus implemented in a semiconductor integrated chip. The apparatus is configured to operate a composite function, comprising a first function and a second function, on a first patch of an image. The apparatus includes a first function operator configured to operate the first function on the group of pixel values to provide a first processed group of pixel values. The apparatus also includes a delay system configured to maintain the first processed group of pixel values for a predetermined period of time to provide a delayed processed group of pixel values. The apparatus further includes a second function operator configured to operate a second function on at least a second processed group of pixels and the delayed processed group to determine an output of the composite function.Type: GrantFiled: November 15, 2013Date of Patent: November 24, 2015Assignee: Linear Algebra Technologies LimitedInventors: David Donohoe, Brendan Barry, David Moloney, Richard Richmond, Fergal Connor
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Patent number: 9146747Abstract: The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.Type: GrantFiled: November 18, 2013Date of Patent: September 29, 2015Assignee: LINEAR ALGEBRA TECHNOLOGIES LIMITEDInventors: David Moloney, Richard Richmond, David Donohoe, Brendan Barry, Cormac Brick, Ovidiu Andrei Vesa
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Publication number: 20150138405Abstract: The disclosed embodiments include an apparatus implemented in a semiconductor integrated chip. The apparatus is configured to operate a composite function, comprising a first function and a second function, on a first patch of an image. The apparatus includes a first function operator configured to operate the first function on the group of pixel values to provide a first processed group of pixel values. The apparatus also includes a delay system configured to maintain the first processed group of pixel values for a predetermined period of time to provide a delayed processed group of pixel values. The apparatus further includes a second function operator configured to operate a second function on at least a second processed group of pixels and the delayed processed group to determine an output of the composite function.Type: ApplicationFiled: November 15, 2013Publication date: May 21, 2015Applicant: LINEAR ALGEBRA TECHNOLOGIES LIMITEDInventors: David DONOHOE, Brendan BARRY, David MOLONEY, Richard RICHMOND, Fergal CONNOR
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Publication number: 20150046677Abstract: The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.Type: ApplicationFiled: November 18, 2013Publication date: February 12, 2015Applicant: LINEAR ALGEBRA TECHNOLOGIES LIMITEDInventors: David MOLONEY, Richard RICHMOND, David DONOHOE, Brendan BARRY
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Publication number: 20150046673Abstract: A vector processor is disclosed including a variety of variable-length instructions. Computer-implemented methods are disclosed for efficiently carrying out a variety of operations in a time-conscious, memory-efficient, and power-efficient manner. Methods for more efficiently managing a buffer by controlling the threshold based on the length of delay line instructions are disclosed. Methods for disposing multi-type and multi-size operations in hardware are disclosed. Methods for condensing look-up tables are disclosed. Methods for in-line alteration of variables are disclosed.Type: ApplicationFiled: August 12, 2014Publication date: February 12, 2015Inventors: Brendan BARRY, Fergal CONNOR, Martin O'RIORDAN, David MOLONEY, Sean POWER
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Publication number: 20150046674Abstract: The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices.Type: ApplicationFiled: August 12, 2014Publication date: February 12, 2015Inventors: Brendan BARRY, Richard RICHMOND, Fergal CONNOR, David MOLONEY
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Publication number: 20150046675Abstract: The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices.Type: ApplicationFiled: August 12, 2014Publication date: February 12, 2015Inventors: Brendan BARRY, Richard RICHMOND, Fergal CONNOR, David MOLONEY
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Publication number: 20150046678Abstract: The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.Type: ApplicationFiled: November 18, 2013Publication date: February 12, 2015Applicant: Linear Algebra Technologies LimitedInventors: David MOLONEY, Richard RICHMOND, David DONOHOE, Brendan BARRY, Cormac BRICK, Ovidiu Andrei VESA
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Publication number: 20140348431Abstract: The present application provides a method of corner detection and an image processing system for detecting corners in an image. The preferred implementation is in software using enabling and reusable hardware features in the underlying vector processor architecture. The advantage of this combined software and programmable processor datapath hardware is that the same hardware used for the FAST algorithm can also be readily applied to a variety of other computational tasks, not limited to image processing.Type: ApplicationFiled: May 21, 2014Publication date: November 27, 2014Applicant: LINEAR ALGEBRA TECHNOLOGIES LIMITEDInventors: Cormac BRICK, Brendan BARRY, Fergal CONNOR, David MOLONEY
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Patent number: 8886760Abstract: Systems and methods of predictive data acquisition are disclosed. A personal proxy server is configured to acquire first data in response to a first request to access the first data and to acquire second data prior to receiving a second request to access the second data. The first request and the second request are received from a common source. The personal proxy server is also configured to store the acquired first data and the acquired second data so that the acquired first data and the acquired second data are accessible to the personal proxy server.Type: GrantFiled: June 30, 2009Date of Patent: November 11, 2014Assignee: Sandisk Technologies Inc.Inventors: Fabrice Jogand-Coulomb, Phillip Jeffrey Balma, Pascal Achille Caillon, Aviv Alluf, Brendan Barry Kavanagh, Kurt Forsyth Webster, Elliot Broadwin, James Frederick Schram, Henry Ricardo Hutton
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Publication number: 20100332586Abstract: Systems and methods of predictive data acquisition are disclosed. A personal proxy server is configured to acquire first data in response to a first request to access the first data and to acquire second data prior to receiving a second request to access the second data. The first request and the second request are received from a common source. The personal proxy server is also configured to store the acquired first data and the acquired second data so that the acquired first data and the acquired second data are accessible to the personal proxy server.Type: ApplicationFiled: June 30, 2009Publication date: December 30, 2010Inventors: Fabrice Jogand-Coulomb, Phillip Jeffrey Balma, Pascal Achille Caillon, Aviv Alluf, Brendan Barry Kavanagh, Kurt Forsyth Webster, Elliot Broadwin, James Frederick Schram, Henry Ricardo Hutton