Abstract: A control unit for DASD operation to transfer data between the device and a buffer and between a channel and a buffer. In that manner the channel and device are enabled to transfer data independently of each other. Mechanisms are provided for communication between the channel interface process in the control unit and the device interface process in the control unit. Some of these mechanisms are stored with the record in the buffer and others are stored in control storage. Principle communicating mechanisms include a device record pointer, a channel record pointer, a next operation field, a device state indicator, record control flags, and two buffer pointers.

Abstract: A technique is described for assuring the global identification and management of interchangeable data storage devices in a data processing system, assuring the integrity of data storage devices after shutdowns or failures and providing these capabilities without changing any current system or application software on the host. This technique also provides high availability of data storage devices by swapping a failing data storage device with a good data storage device without host intervention.

Abstract: A cached DASD controller is illustrated which is attached to a high speed serial channel, such as an optical fiber channel. The data rate of the serial channel is much greater than the data rate of a DASD connected to the controller. The serial channel has a relatively long propagation time such that synchronous operations between the host processor 10 and the DASD cannot be efficiently performed. Operation of a data transfer, whether read or write between the host processor 10 and the DASD is monitored. Whenever reading a copy of the track contents stored in cache or the DASD reaches either an index mark, a break point from a roll mode operation or certain write operations occur resulting in predetermined data being stored in cache, then a GOCACHE flag is set in a control portion of the controller. The device operations are then momentarily idled while cache to host processor data transfer operations are enabled.

Abstract: A data processing system includes a plurality of host systems and peripheral subsystems, particularly data storage subsystems. Each of the data storage subsystems includes a plurality of control units attaching a plurality of data storage devices such as direct access storage devices (DASD) for storing data on behalf of the various host systems. Each of the control units have a separate storage path for accessing the peripheral data storage devices using dynamic pathing. The storage paths can be clustered into power clusters. Maintenance personnel acting through maintenance panels on either the control units or the peripheral data storage devices activate the subsystem to request reconfiguration of the subsystem from all of the host systems connected top the subsystem. The host systems can honor the request or reject it based upon diverse criteria. Upon each of the host systems approving the reconfiguration, the subsystem 13 is reconfigured for maintenance purposes.

Abstract: A technique is described for performing a fast write operation. A host write request, which would normally be serviced by an immediate physical write to a data storage device, is instead written to cache and nonvolatile storage in the data storage device controller. Then, the controller signals the host that the write operation is complete and does not update the physical data storage device until later. A journal log is also used to provide recovery capability in the event of system failure. This technique provides high performance for the units' operation while assuring integrity by keeping two copies of the write operation until the physical update transpires.

Abstract: A hierarchical communication system has multipaths for different levels of the heirarchy, each set of paths is assigned a criticalness to the successful operation of the system. Error rates for all of the paths are monitored. A threshold for defining an unusable data path is based upon the criticalness of the path to successful operation. That is, the more critical the path, the higher the error rate that will be sustained. A specific embodiment employs shift registers for indicating the error rate of the last predetermined number of usages of the given paths. A mass storage system employing the error-rate system is described.