Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.

Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.

Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.

Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.

Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.

Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.

Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.

Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.

Abstract: A method and apparatus for matching parent processor address translations to media processors'address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.

Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.

Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.

Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.

Abstract: Embodiments of the present invention blend frames over a specified spatial and temporal extent to produce a smoothly animated appearance at a reduced frame rate. As the window moves further or closer to the viewer, motion blur may be accomplished by a combination of spatial and temporal averaging. Spatial averaging is used in conjunction with temporal averaging to reduce the rate at which images, including desktop images, are composed and to reduce the amount of graphics memory bandwidth needed for the composition.

Abstract: Embodiments of the present invention blend frames over a specified temporal window to produce a smooth appearance at a reduced frame rate. As the window moves further or closer to the viewer, motion blur may be accomplished by temporal averaging. In particular, the temporal average is used to blend image information for a predefined/brief interval before and after the time of the output frame, retaining all of the image information, but in a slightly blurred form. After the relevant image information is retained, frames may be displayed at a reduced output rate while retaining sufficient information to reproduce a smoothly moving animation sequence.

Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.

Abstract: In some embodiments, a method includes generating blurred copies of an object by applying multi-texturing to the object during one pass through a graphics processing pipeline. In some embodiments, a graphics pipeline includes a texture memory and a graphics processor coupled to the texture memory. The texture memory provides a location to store texture information. The graphics processor provides processor to process the texture information by shifting and blending the texture information in one pass through the graphics processor to obtain shifted and blended texture information.

Abstract: Transactions are scheduled over a half duplex link between a first device, such as an IO unit, and a second device, such as a memory controller. Information flowing over the half duplex link is divided into a plurality of service periods, and an isochronous transaction, such as an isochronous memory read or write, is scheduled in a service period N if the isochronous transaction is ready to be serviced before service period N at the first or second device. An asynchronous transaction ready to be serviced at the first or second device, such as an asynchronous memory read or write, is scheduled if no isochronous transaction is ready to be serviced.

Abstract: Transactions are scheduled over a half duplex link between a first device, such as an IO unit, and a second device, such as a memory controller. Information flowing over the half duplex link is divided into a plurality of service periods, and an isochronous transaction, such as an isochronous memory read or write, is scheduled in a service period N if the isochronous transaction is ready to be serviced before service period N at the first or second device. An asynchronous transaction ready to be serviced at the first or second device, such as an asynchronous memory read or write, is scheduled if no isochronous transaction is ready to be serviced.

Abstract: A method includes setting a contention scheme for an asynchronous bus such that the contention delay of isochronous transactions on the bus is bounded, and establishing an isochronous interface between at least two devices, the isochronous interface supporting an X-T contract. A number of isochronous transactions and corresponding return transactions delivered across the bus is measured during a specified time interval.

Abstract: A computer system provides for the use of isochronous interrupts by devices coupled with the system. Isochronous interrupt requests are received by an interrupt controller during a first time period, recorded, and executed during a second time period. The devices are equipped to handle the delay in interrupt execution. The interrupt controller is set to service isochronous interrupts on a periodic basis. The interrupt controller may flexibly schedule the execution of the isochronous interrupt request at any time during the second time period.