Abstract: Transactions are scheduled over a half duplex link between a first device and a second device. Information flowing over the half duplex link is divided into a plurality of service periods. According to one embodiment of the present invention, the transfer of a read request transaction, from the first device to the second device, is scheduled in one service period. The transfer of a write transaction, from the first device to the second device, is scheduled such that the write transaction will not be transferred across the half duplex link in the same service period as returning memory read data is transferred across the half duplex link. According to another embodiment of the present invention, a first transaction associated with a first agent is scheduled in a first service period according to a global schedule. The global schedule associates the first service period with the first agent.

Abstract: Access to a memory is arbitrated by a memory arbiter. A plurality of first counters in the memory arbiter decrements service periods associated with isochronous memory requests, and a second counter decrements a service period associated with asynchronous memory requests, with the service periods for the first and second memory requests together comprising a schedule period. A scheduler logic circuit receives isochronous and asynchronous memory requests and generates a grant signal to service a received asynchronous request during the schedule period if time remains in the second counter or if there are no pending isochronous memory requests.

Abstract: Access to a memory is arbitrated by defining a schedule period having service periods for isochronous and asynchronous memory requests. Received isochronous requests are serviced during their respective service periods, and if an asynchronous request is received during an isochronous service period , the isochronous service period is suspended and the asynchronous request is serviced, provided that time remains in the asynchronous service period or there is no isochronous request pending. Otherwise, service of the asynchronous request is delayed until the next schedule period. Service time for isochronous request are therefore guaranteed and scheduled around asynchronous memory request. If there are any maintenance events signaled, the service period for the asynchronous request may be correspondingly decreased while the maintenance event is performed.

Abstract: Transactions are scheduled over a half duplex link between a first device and a second device. Information flowing over the half duplex link is divided into a plurality of service periods. According to one embodiment of the present invention, the transfer of a read request transaction, from the first device to the second device, is scheduled in one service period. The transfer of a write transaction, from the first device to the second device, is scheduled such that the write transaction will not be transferred across the half duplex link in the same service period as returning memory read data is transferred across the half duplex link. According to another embodiment of the present invention, a first transaction associated with a first agent is scheduled in a first service period according to a global schedule. The global schedule associates the first service period with the first agent.

Abstract: Access to a memory is arbitrated by a memory arbiter. A plurality of first counters in the memory arbiter decrements service periods associated with isochronous memory requests, and a second counter decrements a service period associated with asynchronous memory requests, with the service periods for the first and second memory requests together comprising a schedule period. A scheduler logic circuit receives isochronous and asynchronous memory requests and generates a grant signal to service a received asynchronous request during the schedule period if time remains in the second counter. If there are any maintenance events signaled, the memory arbiter may correspondingly decrease the service period for the asynchronous request while the maintenance event is performed.

Abstract: A method includes setting a contention scheme for an asynchronous bus such that the contention delay of isochronous transactions on the asynchronous bus is bounded. A first device is coupled to the asynchronous bus to receive an isochronous transaction from an isochronous device and output the isochronous transaction to the asynchronous bus. A second device is coupled to the asynchronous bus to receive the isochronous transaction from the asynchronous bus and output the isochronous transaction to a third device.

Abstract: A high throughput memory access port is provided. The port includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The port allows memory read and write requests to be pipelined in order to hide the effects of memory access latency. In particular, the port allows bus transactions to be performed in either a non-pipelined mode, such as provided by PCI, or in a pipelined mode. In the pipelined mode, one or more additional memory access requests are permitted to be inserted between a first memory access request and its corresponding data transfer. In contrast, in the non-pipelined mode, an additional memory access request cannot be inserted between a first memory access request and its corresponding data transfer.

Abstract: Isochronous information is transferred between an IO device and a first buffer (N) of a plurality of buffers in a system memory. The isochronous information stored in the plurality of buffers is also stored in a memory cache accessible to a system processor. The state of the memory cache is managed according to an isochronous “X-T” contract that is independent of the “X-T” contact with which data are moved between the IO device and system memory. Further, data associated with a given buffer are moved into and out of the memory cache substantially simultaneously with the transfer of isochronous information between the IO device and other buffers in the system memory.

Abstract: An architecture for the isochronous transfer of information within a computer system in which a first isochronous stream of information is transferred, and asynchronous information is transferred independently from the transfer of the first stream. A translation is performed between the first stream and a second isochronous stream of information, and the second stream transfers information at a rate substantially the same as the rate at which the first stream transfers information. The second stream and the asynchronous information are concurrently transferred. In another embodiment of the present invention, a first isochronous stream of information is transferred, and the first stream is divided into a plurality of first service periods. Each first service period has a first duration and contains a first amount of information. A second isochronous stream of information is transferred independently from the transfer of the first stream.

Abstract: An architecture is provided for isochronous access to memory in a system in which a stream of information may be sent to a memory unit. The stream is divided into a plurality of service periods with a specified maximum amount of information in selected service periods, and selected service periods have a first amount of information associated with asynchronous information and a second amount of information associated with isochronous information. In addition to sending a stream of information, a request for isochronous information from the memory unit may be sent. In this case, a stream of the requested information may be received from a memory unit a predetermined number of service periods after the sending of the request.

Abstract: A high throughput memory access interface is provided. The interface includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The interface allows memory access requests to be performed in such a manner that only portions of an access request are required to be transmitted to the target device for certain bus transactions. Each access request includes command bits, address bits, and length bits. In the initiating device, each access request is separated into three segments, which are stored in separate registers in both the initiating device and the target device. Only the segment which contains the lowest order address bits and the length bits is required by the target device to initiate the bus transaction. Thus, if either of the other two segments has not changed since the previous access request, then such segment or segments are not transmitted to the target.