Patents by Inventor Brent S. Krusor
Brent S. Krusor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11122683Abstract: Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed.Type: GrantFiled: November 14, 2018Date of Patent: September 14, 2021Assignee: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Tse Nga Ng, Ping Mei, Brent S. Krusor, Gregory L. Whiting, Steven E. Ready, Janos Veres
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Patent number: 10847384Abstract: Development of smart objects with electronic functions requires integration of printed components with IC chips or dies. Conventional chip or die bonding including wire bonding, flip chip bonding, and soldering may not be applicable to chip or die attachment on low temperature plastic surfaces used in physical objects. Printing conductive connection traces requires a smooth interface between contact pads of a chip and the surface of the physical object. In order to address this issue of chip/die attachment to a physical object, this disclosure provides embodiments to construct a fixture on a chip or die for attachment and electrical connection onto a physical object by printing operations and/or ACF bonding methods.Type: GrantFiled: May 31, 2017Date of Patent: November 24, 2020Assignee: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Ping Mei, Brent S. Krusor, Steven E Ready
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Patent number: 10466193Abstract: A printed resistive gas detector configuration that is simple, inexpensive and compact, fabricated for incorporation into an electronic device, such as an electronic computing and/or communication device, the printed resistive gas detector configuration designed to continuously monitor for predetermined types of gasses. The printed resistive gas detector configuration manufactured by the use of printing technology to print on a flexible substrate.Type: GrantFiled: March 1, 2017Date of Patent: November 5, 2019Assignee: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Robert A. Street, David Eric Schwartz, Ping Mei, Brent S. Krusor, Jonathan Rivnay, Yong Zhang, Gregory L. Whiting, Sivkheng Kor, Steven E. Ready
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Patent number: 10420222Abstract: Methods and system which eliminate steps in the mounting a discrete device to an electronic circuit using a conductive film, shortening the time required to attach each discrete device. The methods place a discrete device onto the conductive tape and partially cure portions of the adhesive. The discrete device is then removed from the conductive tape along with the adhesive and conductive particles which have been transferred onto the contact pads of the discrete device. The discrete device is then placed on the substrate and aligned. Pressure and heat are applied to complete the bond.Type: GrantFiled: April 20, 2017Date of Patent: September 17, 2019Assignee: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Brent S. Krusor, Ping Mei
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Patent number: 10388874Abstract: Electronic devices having two or more conductive contacts or terminals and methods of making the same. Including having a conducting interconnect line coated with an insulator stack (functionalized to be hydrophobic), cut—simultaneously allowing for one step, self-aligned, patterning of formed conducting contacts and the insulation stack. The combination of the cut in the insulation, along with the low surface energy of the insulating surface allow for active material to be deposited at the cut site defining the channel.Type: GrantFiled: March 30, 2017Date of Patent: August 20, 2019Assignee: Palo Alto Research Center IncorporatedInventors: Jonathan Rivnay, Ping Mei, Brent S. Krusor
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Patent number: 10349528Abstract: A material deposition system and method is disclosed for depositing material onto raised features on a surface of a substrate. The material deposition system and method are a contact deposition or printing system and method, which employs biased rollerball to deposit the material as it travels along the substrate and over the raised features.Type: GrantFiled: February 21, 2017Date of Patent: July 9, 2019Assignee: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Brent S. Krusor, Ping Mei
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Publication number: 20190124757Abstract: Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed.Type: ApplicationFiled: November 14, 2018Publication date: April 25, 2019Applicant: Palo Alto Research Center IncorporatedInventors: Tse Nga Ng, Ping Mei, Brent S. Krusor, Gregory L. Whiting, Steven E. Ready, Janos Veres
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Patent number: 10206288Abstract: A hybrid electronic assembly includes a substrate having conductive circuit tracings, and includes at least one opening defined within length and width dimensions of the substrate. An electronic circuit component which has conductive circuit tracings, and is located within the at least one opening of the substrate. An alignment area where a first surface of the substrate and a first surface of the electronic circuit component are aligned in a substantially planar flat relationship with the electronic circuit component. A non-alignment area where a second surface of the substrate and a second surface of the electronic circuit component are in a non-aligned relationship.Type: GrantFiled: December 10, 2015Date of Patent: February 12, 2019Assignee: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Ping Mei, Gregory L. Whiting, Brent S. Krusor
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Patent number: 10165677Abstract: Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed.Type: GrantFiled: December 10, 2015Date of Patent: December 25, 2018Assignee: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Ping Mei, Tse Nga Ng, Brent S. Krusor, Gregory L. Whiting, Steven E. Ready, Janos Veres
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Publication number: 20180350729Abstract: Development of smart objects with electronic functions requires integration of printed components with IC chips or dies. Conventional chip or die bonding including wire bonding, flip chip bonding, and soldering may not be applicable to chip or die attachment on low temperature plastic surfaces used in physical objects. Printing conductive connection traces requires a smooth interface between contact pads of a chip and the surface of the physical object. In order to address this issue of chip/die attachment to a physical object, this disclosure provides embodiments to construct a fixture on a chip or die for attachment and electrical connection onto a physical object by printing operations and/or ACF bonding methods.Type: ApplicationFiled: May 31, 2017Publication date: December 6, 2018Applicant: Palo Alto Research Center IncorporatedInventors: Ping Mei, Brent S. Krusor, Steven E. Ready
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Patent number: 10147702Abstract: The present application provides methods, systems and devices for simultaneously bonding multiple semiconductor chips of different height profiles on a flexible substrate.Type: GrantFiled: October 24, 2016Date of Patent: December 4, 2018Assignee: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Brent S. Krusor, Ping Mei
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Patent number: 10141668Abstract: Printed flexible hybrid electronic systems may require electrical interconnection to peripheral elements. For example, a printed sensor tag with wireless communication may need to connect to a printed sensing electrode on a separated substrate. Frequently, it is desired that these interconnections be detachable in order to replace peripheral elements or to facilitate low cost and simplified assembly, test, rework, and repair. Unlike conventional printed circuit board, mounting a connector on a flexible substrate for detachable connection is challenging due to low temperature requirements. Provide is a teaching of a thin film or form of electrical connection for two circuit elements on separate flexible substrates. The connection is detachable and re-attachable for replacing different circuit elements. The detachable connection is in embodiments realized by selective deposition of fine patterns of conductive materials and non-conductive repositionable pressure-sensitive adhesive.Type: GrantFiled: July 6, 2017Date of Patent: November 27, 2018Assignee: Palo Alto Research Center IncorporatedInventors: Ping Mei, David Eric Schwartz, Brent S. Krusor
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Publication number: 20180310415Abstract: Methods and system which eliminate steps in the mounting a discrete device to an electronic circuit using a conductive film, shortening the time required to attach each discrete device. The methods place a discrete device onto the conductive tape and partially cure portions of the adhesive. The discrete device is then removed from the conductive tape along with the adhesive and conductive particles which have been transferred onto the contact pads of the discrete device. The discrete device is then placed on the substrate and aligned. Pressure and heat are applied to complete the bond.Type: ApplicationFiled: April 20, 2017Publication date: October 25, 2018Applicant: Palo Alto Research Center IncorporatedInventors: Brent S. Krusor, Ping Mei
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Patent number: 10109410Abstract: A method for forming an out of plane structure includes depositing a layer of an elastic material on a substrate wherein the elastic material has an intrinsic stress profile. The layer of elastic material is photolithographically patterned into at least two spaced-apart elastic members. An electrically non-conductive tether layer joins the elastic members. A portion of the substrate is etched under the elastic members to release a free end of each elastic member, while leaving an anchor portion of each elastic member fixed to the substrate. The stress profile of the elastic members biases the free ends of the elastic members away from the substrate forming loops. The structure is electroplated by applying a voltage having a first polarity between an anode and the structure while the structure is in an electroplating bath. Subsequent to the electroplating, the polarity of the voltage between the anode and the structure is reversed.Type: GrantFiled: January 17, 2017Date of Patent: October 23, 2018Assignee: Palo Alto Research Center IncorporatedInventors: Brent S. Krusor, Christopher L. Chua
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Publication number: 20180284059Abstract: Electronic devices having two or more conductive contacts or terminals and methods of making the same. Including having a conducting interconnect line coated with an insulator stack (functionalized to be hydrophobic), cut—simultaneously allowing for one step, self-aligned, patterning of formed conducting contacts and the insulation stack. The combination of the cut in the insulation, along with the low surface energy of the insulating surface allow for active material to be deposited at the cut site defining the channel.Type: ApplicationFiled: March 30, 2017Publication date: October 4, 2018Applicant: Palo Alto Research Center IncorporatedInventors: Jonathan Rivnay, Ping Mei, Brent S. Krusor
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Publication number: 20180252659Abstract: A printed resistive gas detector configuration that is simple, inexpensive and compact, fabricated for incorporation into an electronic device, such as an electronic computing and/or communication device, the printed resistive gas detector configuration designed to continuously monitor for predetermined types of gasses. The printed resistive gas detector configuration manufactured by the use of printing technology to print on a flexible substrate.Type: ApplicationFiled: March 1, 2017Publication date: September 6, 2018Applicant: Palo Alto Research Center IncorporatedInventors: Robert A. Street, David Eric Schwartz, Ping Mei, Brent S. Krusor, Jonathan Rivnay, Yong Zhang, Gregory L. Whiting, Sivkheng Kor, Steven E. Ready
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Publication number: 20180236480Abstract: A material deposition system and method is disclosed for depositing material onto raised features on a surface of a substrate. The material deposition system and method are a contact deposition or printing system and method, which employs biased rollerball to deposit the material as it travels along the substrate and over the raised features.Type: ApplicationFiled: February 21, 2017Publication date: August 23, 2018Applicant: Palo Alto Research Center IncorporatedInventors: Brent S. Krusor, Ping Mei
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Publication number: 20180204662Abstract: A method for forming an out of plane structure includes depositing a layer of an elastic material on a substrate wherein the elastic material has an intrinsic stress profile. The layer of elastic material is photolithographically patterned into at least two spaced-apart elastic members. An electrically non-conductive tether layer joins the elastic members. A portion of the substrate is etched under the elastic members to release a free end of each elastic member, while leaving an anchor portion of each elastic member fixed to the substrate. The stress profile of the elastic members biases the free ends of the elastic members away from the substrate forming loops. The structure is electroplated by applying a voltage having a first polarity between an anode and the structure while the structure is in an electroplating bath. Subsequent to the electroplating, the polarity of the voltage between the anode and the structure is reversed.Type: ApplicationFiled: January 17, 2017Publication date: July 19, 2018Inventors: Brent S. Krusor, Christopher L. Chua
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Publication number: 20180114772Abstract: The present application provides methods, systems and devices for simultaneously bonding multiple semiconductor chips of different height profiles on a flexible substrate.Type: ApplicationFiled: October 24, 2016Publication date: April 26, 2018Applicant: Palo Alto Research Center IncorporatedInventors: Brent S. Krusor, Ping Mei
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Patent number: 9947611Abstract: Disclosed is an integrated circuit arrangement including a two sided circuit board, having a first surface and a second surface. A plurality of electrical conductors is incorporated as part of the two sided circuit board. An array of through holes extend through the first surface and the second surface, arranged in a pattern and are configured to provide a common electrical connection area, wherein the common electrical connection area is associated with a portion of a particular one of the plurality of electrical conductors.Type: GrantFiled: January 29, 2016Date of Patent: April 17, 2018Assignee: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Ping Mei, Brent S. Krusor, David K. Biegelsen