Abstract: Paging scheme for a microcontroller for extending available register space. A method for paging at least a portion of an address space in a processing system is disclosed. A plurality of addressable memory locations are provided arranged in pages. Each of the addressable memory locations in each of the pages occupies at least a portion of the address space of the processing system and has an associated address in the address space of the processing system. A page pointer is stored in a storage location to define the desired page and then an address is generated in the at least a portion of the address space of the processing system. At least one of the addressable memory locations in at least two of the pages with the same address has identical information stored therein.

Abstract: Method and apparatus for accessing paged memory with indirect addressing. A a method for changing pages of memory in an indirect addressed memory having a plurality of addressable locations therein is diclosed. An index indicative of the page of the memory being addressed is stored in a memory location. The memory is addressed with a direct address that selects one or more of the addressable locations in the addressed page of memory. An interrupt is received from a resource capable of generating an interrupt, which interrupt has associated therewith a defined one of the pages of memory. In response to generation of the interrupt, the value of the stored index t is changed o an index associated with the defined one of the pages of memory associated with the resource. In response to receiving a signal indicative of the generated interrupt having been serviced by a system that services interrupts, the stored index is changed to a different index.

Abstract: Method and apparatus for accessing paged memory with indirect addressing. A a method for changing pages of memory in an indirect addressed memory having a plurality of addressable locations therein is diclosed. An index indicative of the page of the memory being addressed is stored in a memory location. The memory is addressed with a direct address that selects one or more of the addressable locations in the addressed page of memory. An interrupt is received from a resource capable of generating an interrupt, which interrupt has associated therewith a defined one of the pages of memory. In response to generation of the interrupt, the value of the stored index t is changed o an index associated with the defined one of the pages of memory associated with the resource.

Abstract: Paging scheme for a microcontroller for extending available register space. A method for paging at least a portion of an address space in a processing system is disclosed. A plurality of addressable memory locations are provided arranged in pages. Each of the addressable memory locations in each of the pages occupies at least a portion of the address space of the processing system and has an associated address in the address space of the processing system. A page pointer is stored in a storage location to define the desired page and then an address is generated in the at least a portion of the address space of the processing system. At least one of the addressable memory locations in at least two of the pages with the same address has identical information stored therein.

Abstract: A device which has been designed and tested to improve the ease and cleanliness of transporting food portions from one place to another. The one-handed operation is simple and intuitive. Portions of food may be sliced from an original whole with the slicing edge and the cutting teeth on the spatula. Food portions may also be freed from being stuck to a serving plate or pan when the wedge shaped risers on the bottom of the spatula portion are slid underneath the food portion. A clamp bar operated by a thumb or a forefinger applies clamping pressure to the food portion while it is being transported, preventing the food from falling off of the spatula and eliminating the need for another device or the use of a finger of the server's other hand to insure that the food portion remains on the spatula while being moved. Especially useful for difficult to serve foods such as pizza, where cheese strings remain attached to the piece being removed and pull it from the spatula.

Abstract: A system and method dynamically process video data received by a video decoder by determining a throttling amount, at a decoder throttling device, based on a measure of computational processing power required to decode at least one bitstream of the video data or the decoder's processing capabilities. The computational processing requirements of the decoder are controlled based on the throttling amount, including reducing the processing performed on the decoded video data prior to displaying a picture associated with the decoded video data. The decoder may reduce the amount of processing by limiting functions of at least one post filter or conversion filter. The computational processing requirements may also be controlled by comparing temporal references of two motion vectors of a picture of the video data, determining which motion vector has a closer temporal distance from the picture being decoded and processing only the motion vector having the closer temporal distance.

Abstract: The invention described herein permits video decoders of varying degrees of computational power to decode bitstreams with varying degrees of visual quality degradation. It does so by reducing processing power requirements of a video decoder based on both bitstream contents and decoder capabilities. One method it uses is the reduction of motion compensation processing by modifying the use or values of motion vectors, such as by turning some motion compensation off, or by limiting the precision of motion vectors during decoding. Another method is by limiting the coefficient processing so as to reduce the computational requirements. Another method is to limit the processing of color components, and another method is by reducing the amount of filtering performed on the decoder's output video pictures.

Abstract: A memory access controller generates memory access commands from memory access requests. A sequence of memory access requests is input and destributed to need-makers. Each need-maker determines the memory access command needed by it's respective memory access request. These needs are passed to and prioritized by a prioritizer. The desired memory access command is then selected from these prioritized needs according to the requirements of the memory. This can be done by checking each prioritized need against a set of memory rules. The prioritized needs which pass all the required memory rules are then passed to a command output selector which selects the most appropriate one, resulting in the desired memory access command.

Abstract: The present invention discloses an MPEG decoder for reproducing moving picture data. A first frame memory (FM0) and a second frame memory (FM1), each of which is composed of 2N slots, are provided. A third frame memory (FM2) is provided which is composed of N+4 slots. Each slot is provided with a memory capacity of eight lines. FM0 and FM1 each have a 1-frame memory capacity for storing reference frames for motion compensation. FM2, on the other hand, has a memory capacity of half a frame+32 lines for B-PICTURE interlace conversion. A slot control memory (SM) is further provided which is composed of 2N+6 words each of which stores a respective slot number of FM2. For an output section to read the slots of FM2 in the correct order, the contents of SM are updated by an control section at the time of the writing of FM2 by a decoding section.

Abstract: The invention described herein is a versatile variable length coder with a small table side. The size of the table was reduced by the use of a linked list of groups of like valued run-level code words for the code table, the effect of which is the ability to store and access the Huffman code words without reserving space for the holes in the Huffman tables. Traversing the linked list as the fixed length codes are input has the effect of eliminating the requirement that sequences of codes are run-level fixed length coded before being variable length coded. This simplifies encoder architectures and circuits. The result is the dramatic reduction in size of a programmable variable length coder, making them suitable for implementation in VLSI implementations of digital audio and video codecs.

Abstract: A method for calculating the pixel values of a sub-pixel accuracy motion compensated block of video pixels from one or two reference blocks, as is required in typical digital video compression and decompression systems uses a minimal amount of temporary storage memory resulting in a compact architecture suited for inexpensive consumer applications. This method utilizes a pixel pipeline within a block line pipeline to calculate the half pel accurate reference blocks and to average two blocks to result in a prediction block of pixels. The lines from each reference block are input to the invention alternately resulting in reduced memory requirements.