Patents by Inventor Brett Tischler
Brett Tischler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7107494Abstract: A processing system comprising: i) processor core; ii) a memory; iii) N peripheral devices; and iv) a communication bus coupled to the processor core, the memory and the N peripheral devices that transfers bus request packets between the processor core, the memory, and the N peripheral devices. The communication bus comprises debug circuitry for capturing bus transaction data associated with a bus transaction between a first of the peripheral devices and a second of the peripheral devices and transferring the captured bus transaction data to an external test device.Type: GrantFiled: April 29, 2003Date of Patent: September 12, 2006Assignee: Advanced Micro Devices, Inc.Inventor: Brett A. Tischler
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Patent number: 7043593Abstract: A master unit and a slave unit in a data processor are coupled together by a data bus. The master unit sends data transactions to the slave unit through the data bus and the slave unit executes the data transactions. The present invention comprises an apparatus and method for executing a data transaction either (1) by executing the data transaction “in order” with respect to other data transactions received by the slave unit, or (2) by executing the data transaction “out of order” with respect to other data transactions received by the slave unit. The master unit assigns a priority identifier to each data transaction. The slave unit reads the priority identifier to determine whether to execute the data transaction “in order” or “out of order” with respect to the other data transactions.Type: GrantFiled: April 29, 2003Date of Patent: May 9, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Brett A. Tischler, Kenneth J. Kotlowski
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Patent number: 7020741Abstract: For use with a memory controller in a data processor that is capable of executing memory refresh requests to refresh a memory of the data processor, an apparatus and method is disclosed for scheduling execution of the memory refresh requests. The apparatus comprises a periodic memory refresh hint unit that is capable of sending to the memory controller a data signal that comprises a periodic memory refresh hint. The periodic memory refresh hint informs the memory controller of an optimal time for a memory refresh to occur. The memory controller may immediately execute a memory refresh request when it arrives or delay the execution of the memory refresh request until a more opportune time. This feature enables the memory controller to reduce memory access latency in scheduling memory transactions.Type: GrantFiled: April 29, 2003Date of Patent: March 28, 2006Assignee: Advanced Micro Devices, Inc.Inventor: Brett A. Tischler
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Patent number: 7007188Abstract: A system clock circuit that provides a high-speed reference clock signal for operating an integrated circuit. The system clock circuit comprises a frequency combiner circuit that receives a first external clock signal having a frequency F1 and a second external clock signal having frequency F2, where F2 is an integer multiple of F1. The second external clock signal is phase-shifted by P degrees with respect to the first external clock signal. The frequency combiner circuit generates from the first and second external clock signals a first output clock signal having an operating frequency that is the sum of F1 and F2. The system clock circuit also comprises a clock selection circuit that selectively applies the first output clock signal to the integrated circuit.Type: GrantFiled: April 29, 2003Date of Patent: February 28, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Brett A. Tischler, Steven J. Kommrusch
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Patent number: 6924810Abstract: A dynamically configurable portion of a cache shared between central processing and graphics units in a highly integrated multimedia processor is engaged as a secondary level in a hierarchical texture cache architecture. The graphics unit includes a small multi-ported L1 texture cache local to its 2D/3D pipeline that is backed by the relatively large, single ported portion of the shared cache. Leveraging the shared cache as a secondary level texture cache reduces system memory bandwidth and die size without significant sacrifice in performance.Type: GrantFiled: November 18, 2002Date of Patent: August 2, 2005Assignee: Advanced Micro Devices, Inc.Inventor: Brett A. Tischler
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Patent number: 6912611Abstract: There is disclosed a bus interface unit for transferring data between a plurality of bus devices. The bus interface unit comprises: 1) a first bus device interface comprising: a) a first incoming request bus for receiving request packets from a first one of the plurality of bus devices; b) a first outgoing request bus for transmitting request packets to the first bus device; c) a first incoming data bus for receiving data packets from the first bus device; and d) a first outgoing data bus for transmitting data packets to the first bus device; and 2) a second bus device interface comprising: a) a second incoming request bus for receiving request packets from a second one of the plurality of bus devices; b) a second outgoing request bus for transmitting request packets to the second bus device; c) a second incoming data bus for receiving data packets from the second bus device; and d) a second outgoing data bus for transmitting data packets to the second bus device.Type: GrantFiled: April 30, 2001Date of Patent: June 28, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Kenneth James Kotlowski, Brett A. Tischler
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Publication number: 20040225781Abstract: There is disclosed a bus interface unit for transferring data between a plurality of bus devices. The bus interface unit comprises: 1) a first bus device interface comprising: a) a first incoming request bus for receiving request packets from a first one of the plurality of bus devices; b) a first outgoing request bus for transmitting request packets to the first bus device; c) a first incoming data bus for receiving data packets from the first bus device; and d) a first outgoing data bus for transmitting data packets to the first bus device; and 2) a second bus device interface comprising: a) a second incoming request bus for receiving request packets from a second one of the plurality of bus devices; b) a second outgoing request bus for transmitting request packets to the second bus device; c) a second incoming data bus for receiving data packets from the second bus device; and d) a second outgoing data bus for transmitting data packets to the second bus device.Type: ApplicationFiled: April 30, 2001Publication date: November 11, 2004Inventors: Kenneth James Kotlowski, Brett A. Tischler
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Patent number: 6813673Abstract: In a method and system for transferring data between a plurality of bus devices, a bus interface unit includes a first bus device interface (FBDI), a second bus device interface (SBDI), and an arbitration circuit. Each of the FBDI and SBDI includes a corresponding incoming and outgoing request bus for receiving and transmitting request packets from a corresponding one of the plurality of bus devices. Similarly, each of the EBDI and SBDI also includes a corresponding incoming and outgoing data bus for receiving and transmitting data packets from the corresponding one of the plurality of bus devices. The arbitration circuit is capable of determining priority level associated with corresponding request packets received from the FBDI and the SBDI respectively.Type: GrantFiled: April 30, 2001Date of Patent: November 2, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Kenneth James Kotlowski, Brett A. Tischler
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Patent number: 6801207Abstract: A highly integrated multimedia processor employs a shared cache between tightly coupled central processing and graphics units to provide the graphics unit access to data retrieved from system memory or data processed by the central processing unit before the data is written-back or written-through to system memory, thus reducing system memory bandwidth requirements. Regions in the shared cache can also be selectively locked down thereby disabling eviction or invalidation of a selected region, to provide the graphics unit with a local scratchpad area for applications such as, but not limited to, temporary video line buffering storage for filter applications and composite buffering for blending texture maps in multi-pass rendering.Type: GrantFiled: October 9, 1998Date of Patent: October 5, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Brett A. Tischler, Carl D. Dietz, David F. Bremner, David T. Harper
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Patent number: 6785758Abstract: There is disclosed a bus interface unit for transferring machine specific register (MSR) requests between a plurality of bus devices. The bus interface unit comprises: 1) a plurality of input ports for receiving incoming MSR requests from the plurality of bus devices; 2) a plurality of output ports for transmitting data to the plurality of bus devices; and 3) a controller for reading N routing associated with a first received MSR request and comparing a first identification (ID) value in a predetermined M-bit field in the N routing bits to a first designated value. The controller, in response to a determination that the first ID value does not equal the first designated value: 1) realigns the N routing bits such that remaining ones of the N-M bits outside the predetermined M-bit field are moved into the predetermined M-bit field and 2) transmits the realigned N routing bits via a first one of the plurality of output ports identified by the first ID value.Type: GrantFiled: June 1, 2001Date of Patent: August 31, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Kenneth James Kotlowski, Brett A. Tischler
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Patent number: 6763415Abstract: A bus interface unit for transferring data between a plurality of bus devices. The bus interface unit comprises: 1) a destination prediction circuit for predicting a predicted destination bus device associated with a first incoming bus access request received from a requesting one of the plurality of bus devices; 2) an arbitration circuit coupled to the destination prediction circuit and for arbitrating the first incoming bus access request based on the predicted destination bus device; and 3) an address determination circuit for calculating an actual destination bus device at least partially simultaneously with the arbitration of the first incoming bus access request and determining if the calculated actual destination bus device matches the predicted destination bus device.Type: GrantFiled: June 8, 2001Date of Patent: July 13, 2004Assignee: Advanced Micro Devices, Inc.Inventor: Brett A. Tischler
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Patent number: 6591347Abstract: A dynamically configurable replacement technique in a unified or shared cache reduces domination by a particular functional unit or an application such as unified instruction/data caching by limiting the eviction ability to selected cache regions based on over utilization of the cache by a particular functional unit or application. A specific application includes a highly integrated multimedia processor employing a tightly coupled shared cache between central processing and graphics units wherein the eviction ability of the graphics unit is limited to selected cache regions when the graphics unit over utilizes the cache. Dynamic configurability can take the form of a programmable register that enables either one of a plurality of replacement modes based on captured statistics such as measurement of cache misses by a particular functional unit or application.Type: GrantFiled: October 9, 1998Date of Patent: July 8, 2003Assignee: National Semiconductor CorporationInventors: Brett A. Tischler, Rajeev Jayavant
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Patent number: 6483516Abstract: A dynamically configurable portion of a cache shared between central processing and graphics units in a highly integrated multimedia processor is engaged as a secondary level in a hierarchical texture cache architecture. The graphics unit includes a small multi-ported L1 texture cache local to its 2D/3D pipeline that is backed by the relatively large, single ported portion of the shared cache. Leveraging the shared cache as a secondary level texture cache reduces system memory bandwidth and die size without significant sacrifice in performance.Type: GrantFiled: October 9, 1998Date of Patent: November 19, 2002Assignee: National Semiconductor CorporationInventor: Brett A. Tischler
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Publication number: 20020161953Abstract: There is disclosed a bus interface unit for transferring data between a plurality of bus devices.Type: ApplicationFiled: April 30, 2001Publication date: October 31, 2002Inventors: Kenneth James Kotlowski, Brett A. Tischler
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Publication number: 20010049771Abstract: A dynamically configurable replacement technique in a unified or shared cache reduces domination by a particular functional unit or an application such as unified instruction/data caching by limiting the eviction ability to selected cache regions based on over utilization of the cache by a particular functional unit or application. A specific application includes a highly integrated multimedia processor employing a tightly coupled shared cache between central processing and graphics units wherein the eviction ability of the graphics unit is limited to selected cache regions when the graphics unit over utilizes the cache. Dynamic configurability can take the form of a programmable register that enables either one of a plurality of replacement modes based on captured statistics such as measurement of cache misses by a particular functional unit or application.Type: ApplicationFiled: October 9, 1998Publication date: December 6, 2001Inventors: BRETT A. TISCHLER, RAJEEV JAYAVANT