Patents by Inventor Brett W. Busch
Brett W. Busch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11417661Abstract: Some embodiments include an integrated capacitor assembly having a conductive pillar supported by a base, with the conductive pillar being included within a first electrode of a capacitor. The conductive pillar has a first upper surface. A dielectric liner is along an outer surface of the conductive pillar and has a second upper surface. A conductive liner is along the dielectric liner and is included within a second electrode of the capacitor. The conductive liner has a third upper surface. One of the first and third upper surfaces is above the other of the first and third upper surfaces. The second upper surface is at least as high above the base as said one of the first and third upper surfaces. Some embodiments include memory arrays having capacitors with pillar-type first electrodes.Type: GrantFiled: March 1, 2020Date of Patent: August 16, 2022Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Matthew N. Rocklein, Brett W. Busch
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Publication number: 20200203350Abstract: Some embodiments include an integrated capacitor assembly having a conductive pillar supported by a base, with the conductive pillar being included within a first electrode of a capacitor. The conductive pillar has a first upper surface. A dielectric liner is along an outer surface of the conductive pillar and has a second upper surface. A conductive liner is along the dielectric liner and is included within a second electrode of the capacitor. The conductive liner has a third upper surface. One of the first and third upper surfaces is above the other of the first and third upper surfaces. The second upper surface is at least as high above the base as said one of the first and third upper surfaces. Some embodiments include memory arrays having capacitors with pillar-type first electrodes.Type: ApplicationFiled: March 1, 2020Publication date: June 25, 2020Applicant: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Matthew N. Rocklein, Brett W. Busch
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Patent number: 10600788Abstract: Some embodiments include an integrated capacitor assembly having a conductive pillar supported by a base, with the conductive pillar being included within a first electrode of a capacitor. The conductive pillar has a first upper surface. A dielectric liner is along an outer surface of the conductive pillar and has a second upper surface. A conductive liner is along the dielectric liner and is included within a second electrode of the capacitor. The conductive liner has a third upper surface. One of the first and third upper surfaces is above the other of the first and third upper surfaces. The second upper surface is at least as high above the base as said one of the first and third upper surfaces. Some embodiments include memory arrays having capacitors with pillar-type first electrodes.Type: GrantFiled: June 8, 2018Date of Patent: March 24, 2020Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Matthew N. Rocklein, Brett W. Busch
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Publication number: 20190027477Abstract: Some embodiments include an integrated capacitor assembly having a conductive pillar supported by a base, with the conductive pillar being included within a first electrode of a capacitor. The conductive pillar has a first upper surface. A dielectric liner is along an outer surface of the conductive pillar and has a second upper surface. A conductive liner is along the dielectric liner and is included within a second electrode of the capacitor. The conductive liner has a third upper surface. One of the first and third upper surfaces is above the other of the first and third upper surfaces. The second upper surface is at least as high above the base as said one of the first and third upper surfaces. Some embodiments include memory arrays having capacitors with pillar-type first electrodes.Type: ApplicationFiled: July 21, 2017Publication date: January 24, 2019Inventors: GURTEJ S. SANDHU, MATTHEW N. ROCKLEIN, BRETT W. BUSCH
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Publication number: 20190027478Abstract: Some embodiments include an integrated capacitor assembly having a conductive pillar supported by a base, with the conductive pillar being included within a first electrode of a capacitor. The conductive pillar has a first upper surface. A dielectric liner is along an outer surface of the conductive pillar and has a second upper surface. A conductive liner is along the dielectric liner and is included within a second electrode of the capacitor. The conductive liner has a third upper surface. One of the first and third upper surfaces is above the other of the first and third upper surfaces. The second upper surface is at least as high above the base as said one of the first and third upper surfaces. Some embodiments include memory arrays having capacitors with pillar-type first electrodes.Type: ApplicationFiled: June 8, 2018Publication date: January 24, 2019Applicant: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Matthew N. Rocklein, Brett W. Busch
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Patent number: 10177152Abstract: Some embodiments include an integrated capacitor assembly having a conductive pillar supported by a base, with the conductive pillar being included within a first electrode of a capacitor. The conductive pillar has a first upper surface. A dielectric liner is along an outer surface of the conductive pillar and has a second upper surface. A conductive liner is along the dielectric liner and is included within a second electrode of the capacitor. The conductive liner has a third upper surface. One of the first and third upper surfaces is above the other of the first and third upper surfaces. The second upper surface is at least as high above the base as said one of the first and third upper surfaces. Some embodiments include memory arrays having capacitors with pillar-type first electrodes.Type: GrantFiled: July 21, 2017Date of Patent: January 8, 2019Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Matthew N. Rocklein, Brett W. Busch
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Publication number: 20160027863Abstract: A method of forming capacitors includes providing a support material over a substrate. The support material is at least one of semiconductive or conductive. Openings are formed into the support material. The openings include at least one of semiconductive or conductive sidewalls. An insulator is deposited along the semiconductive and/or conductive opening sidewalls. A pair of capacitor electrodes having capacitor dielectric there-between is formed within the respective openings laterally inward of the deposited insulator. One of the pair of capacitor electrodes within the respective openings is laterally adjacent the deposited insulator. Other aspects are disclosed, including integrated circuitry independent of method of manufacture.Type: ApplicationFiled: July 2, 2015Publication date: January 28, 2016Applicant: MICRON TECHNOLOGY, INC.Inventors: Brett W. Busch, Mingtao Li, Lequn Jennifer Liu, Kevin R. Shea, Belford T. Coursey, Jonathan T. Doebler
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Publication number: 20160013191Abstract: A capacitor includes a substrate, a multilayer over the substrate, a plurality of container-shaped storage node structures on the semiconductor substrate and surrounded by the multilayer, the storage node structure has a sidewall extending upwardly from the base to the top, where the sidewall includes an upper segment and a lower segment thinner than the upper segment, a capacitor dielectric material along a surface of each storage node structure, and a capacitor electrode material over the capacitor dielectric material.Type: ApplicationFiled: September 21, 2015Publication date: January 14, 2016Inventors: Sanjeev Sapra, Brett W. Busch, Jian Li, Chad Patrick Blessing, Greg Allen Funston
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Patent number: 9230966Abstract: A capacitor includes a substrate, a multilayer over the substrate, a plurality of container-shaped storage node structures on the semiconductor substrate and surrounded by the multilayer, the storage node structure has a sidewall extending upwardly from the base to the top, where the sidewall includes an upper segment and a lower segment thinner than the upper segment, a capacitor dielectric material along a surface of each storage node structure, and a capacitor electrode material over the capacitor dielectric material.Type: GrantFiled: April 9, 2014Date of Patent: January 5, 2016Assignee: NANYA TECHNOLOGY CORP.Inventors: Sanjeev Sapra, Brett W. Busch, Jian Li, Chad Patrick Blessing, Greg Allen Funston
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Publication number: 20150294971Abstract: A capacitor includes a substrate, a multilayer over the substrate, a plurality of container-shaped storage node structures on the semiconductor substrate and surrounded by the multilayer, the storage node structure has a sidewall extending upwardly from the base to the top, where the sidewall includes an upper segment and a lower segment thinner than the upper segment, a capacitor dielectric material along a surface of each storage node structure, and a capacitor electrode material over the capacitor dielectric material.Type: ApplicationFiled: April 9, 2014Publication date: October 15, 2015Applicant: NANYA TECHNOLOGY CORP.Inventors: Sanjeev Sapra, Brett W. Busch, Jian Li, Chad Patrick Blessing, Greg Allen Funston
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Patent number: 9076680Abstract: A method of forming capacitors includes providing a support material over a substrate. The support material is at least one of semiconductive or conductive. Openings are formed into the support material. The openings include at least one of semiconductive or conductive sidewalls. An insulator is deposited along the semiconductive and/or conductive opening sidewalls. A pair of capacitor electrodes having capacitor dielectric there-between is formed within the respective openings laterally inward of the deposited insulator. One of the pair of capacitor electrodes within the respective openings is laterally adjacent the deposited insulator. Other aspects are disclosed, including integrated circuitry independent of method of manufacture.Type: GrantFiled: October 18, 2011Date of Patent: July 7, 2015Assignee: Micron Technology, Inc.Inventors: Brett W. Busch, Mingtao Li, Jennifer Lequn Liu, Kevin R. Shea, Belford T. Coursey, Jonathan T. Doebler
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Patent number: 8691656Abstract: The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure.Type: GrantFiled: September 7, 2011Date of Patent: April 8, 2014Assignee: Micron Technology, Inc.Inventors: Brett W. Busch, David K. Hwang, F. Daniel Gealy
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Patent number: 8512582Abstract: A method of patterning a substrate in accordance with an embodiment of the invention includes forming a plurality of openings within at least one of photoresist and amorphous carbon. The openings are of common outermost cross sectional shape relative one another. Individual of the openings have at least one lateral open dimension having a degree of variability among the plurality. The photoresist with the plurality of openings is exposed to/treated with a plasma effective to both increase the lateral open size of the openings and at least reduce the degree of variability of said at least one open dimension among the openings. Other aspects and implementations are contemplated.Type: GrantFiled: September 15, 2008Date of Patent: August 20, 2013Assignee: Micron Technology, Inc.Inventors: Mark Kiehlbauch, Brett W. Busch, Tuman Earl Allen
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Publication number: 20130093050Abstract: A method of forming capacitors includes providing a support material over a substrate. The support material is at least one of semiconductive or conductive. Openings are formed into the support material. The openings include at least one of semiconductive or conductive sidewalls. An insulator is deposited along the semiconductive and/or conductive opening sidewalls. A pair of capacitor electrodes having capacitor dielectric there-between is formed within the respective openings laterally inward of the deposited insulator. One of the pair of capacitor electrodes within the respective openings is laterally adjacent the deposited insulator. Other aspects are disclosed, including integrated circuitry independent of method of manufacture.Type: ApplicationFiled: October 18, 2011Publication date: April 18, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Brett W. Busch, Mingtao Li, Jennifer Lequn Liu, Kevin R. Shea, Belford T. Coursey, Jonathan T. Doebler
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Publication number: 20110318921Abstract: The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure.Type: ApplicationFiled: September 7, 2011Publication date: December 29, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Brett W. Busch, David K. Hwang, F. Daniel Gealy
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Patent number: 8030168Abstract: The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure.Type: GrantFiled: April 6, 2009Date of Patent: October 4, 2011Assignee: Micron Technology, Inc.Inventors: Brett W. Busch, David K. Hwang, F. Daniel Gealy
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Publication number: 20100065531Abstract: A method of patterning a substrate in accordance with an embodiment of the invention includes forming a plurality of openings within at least one of photoresist and amorphous carbon. The openings are of common outermost cross sectional shape relative one another. Individual of the openings have at least one lateral open dimension having a degree of variability among the plurality. The photoresist with the plurality of openings is exposed to/treated with a plasma effective to both increase the lateral open size of the openings and at least reduce the degree of variability of said at least one open dimension among the openings. Other aspects and implementations are contemplated.Type: ApplicationFiled: September 15, 2008Publication date: March 18, 2010Inventors: Mark Kiehlbauch, Brett W. Busch, Tuman Earl Allen
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Publication number: 20090197386Abstract: The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure.Type: ApplicationFiled: April 6, 2009Publication date: August 6, 2009Inventors: Brett W. Busch, David K. Hwang, F. Daniel Gealy
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Patent number: 7538036Abstract: A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.Type: GrantFiled: August 31, 2005Date of Patent: May 26, 2009Assignee: Micron Technology, Inc.Inventors: Brett W. Busch, Luan C. Tran, Ardavan Niroomand, Fred D. Fishburn, Yoshiki Hishiro, Ulrich C. Boettiger, Richard D. Holscher
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Patent number: 7445990Abstract: A plurality of capacitor electrode openings is formed within capacitor electrode-forming material. A first set of the openings is formed to a depth which is greater within the capacitor electrode-forming material than is a second set of the openings. Conductive first capacitor electrode material is formed therein. A sacrificial retaining structure is formed elevationally over both the first capacitor electrode material and the capacitor electrode-forming material, leaving some of the capacitor electrode-forming material exposed. With the retaining structure in place, at least some of the capacitor electrode-forming material is etched from the substrate effective to expose outer sidewall surfaces of the first capacitor electrode material.Type: GrantFiled: February 24, 2006Date of Patent: November 4, 2008Assignee: Micron Technology, Inc.Inventors: Brett W. Busch, Fred D. Fishburn, James Rominger