Patents by Inventor Brett W. Busch

Brett W. Busch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods of forming a plurality of circuit components and methods of forming a plurality of structures suspended elevationally above a substrate
    Patent number: 7413952
    Abstract: A plurality of capacitor electrode openings is formed within capacitor electrode-forming material. A first set of the openings is formed to a depth which is greater within the capacitor electrode-forming material than is a second set of the openings. Conductive first capacitor electrode material is formed therein. A sacrificial retaining structure is formed elevationally over both the first capacitor electrode material and the capacitor electrode-forming material, leaving some of the capacitor electrode-forming material exposed. With the retaining structure in place, at least some of the capacitor electrode-forming material is etched from the substrate effective to expose outer sidewall surfaces of the first capacitor electrode material.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: August 19, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Brett W. Busch, Fred D. Fishburn, James Rominger
  • Capacitor structures, and DRAM arrays
    Patent number: 7321149
    Abstract: A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: January 22, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Brett W. Busch, Luan C. Tran, Ardavan Niroomand, Fred D. Fishburn, Richard D. Holscher
  • Methods of forming a plurality of capacitors
    Patent number: 7202127
    Abstract: A plurality of capacitor electrode openings is formed within capacitor electrode-forming material. A first set of the openings is formed to a depth which is greater within the capacitor electrode-forming material than is a second set of the openings. Conductive first capacitor electrode material is formed therein. A sacrificial retaining structure is formed elevationally over both the first capacitor electrode material and the capacitor electrode-forming material, leaving some of the capacitor electrode-forming material exposed. With the retaining structure in place, at least some of the capacitor electrode-forming material is etched from the substrate effective to expose outer sidewall surfaces of the first capacitor electrode material.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: April 10, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Brett W. Busch, Fred D. Fishburn, James Rominger
  • Methods of forming openings, and methods of forming container capacitors
    Patent number: 7153778
    Abstract: A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: December 26, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Brett W. Busch, Luan C. Tran, Ardavan Niroomand, Fred D. Fishburn, Yoshiki Hishiro, Ulrich C. Boettiger, Richard D. Holscher