Abstract: The present invention is directed to a method and apparatus of automatic power management control for a Serial ATA interface that utilizes a combination of IOP control and specialized hardware control. The method may include steps as follows. It is determined, preferably based on a value of the Automate bit in a Task File Ram of a Serial ATA interface, whether a Serial ATA device of the Serial ATA interface is being controlled via the IOP or controlled by the specialized Serial ATA automation hardware. When the Serial ATA device is controlled via the IOP, the IOP may decide when to power up/down the Serial ATA interface. When the Serial ATA device is controlled by the specialized Serial ATA automation hardware, the method may proceed as follows. An idle or active condition of a Serial ATA interface utilizing a combination of IOP control and specialized hardware control is then automatically detected.

Abstract: The present invention is directed to a method and apparatus of automatic power management control for a Serial ATA device directly attached to a SAS/SATA host controller. In an exemplary aspect of the present invention, it is determined whether a Serial ATA device is directly attached to a SAS/SATA host controller without using a SAS expander. When it is determined that the Serial ATA device is directly attached to the SAS/SATA host controller, an idle or active condition of a Serial ATA interface including the Serial ATA device and the SAS/SATA host controller is automatically detected. When the Serial ATA interface is in an idle condition, idle time of the Serial ATA interface is measured using a power down counter whose frequency is determined by a programmable register based on an input clock. When a power down counter value is equal to a first value, a request for a Partial power state is asserted, and Serial ATA interface is put into a Partial power state.

Abstract: The present invention is directed to a method and apparatus of automatic power management control for Serial ATA interface. In an exemplary aspect of the present invention, an idle or active condition of a Serial ATA interface including a NCQ Serial ATA device is automatically detected. In this step, it is determined, preferably based on a value of the FPDMA (First Party Direct Memory Access) bit in a Task File Ram of the Serial ATA interface, whether the NCQ Serial ATA device is in a FPDMA Data Phase. When the NCQ Serial ATA device is in a FPDMA Data Phase, the Serial ATA interface is active (i.e., not idle). When Serial ATA is in an idle condition, idle time of Serial ATA interface is measured using a power down counter whose frequency is determined by a programmable register based on an input clock. When a power down counter value is equal to a first value, a request for a Partial power state is asserted, and Serial ATA interface is put into a Partial power state.

Abstract: The present invention is directed to a method and apparatus of automatic power management control for Serial ATA interface. In an exemplary aspect of the present invention, an idle or active condition of Serial ATA interface is automatically detected. When Serial ATA is in an idle condition, idle time of Serial ATA interface is counted using a power down counter whose frequency is determined by a programmable register based on input clock. When a power down counter value is equal to a first value, a request for a Partial power state is asserted, and Serial ATA interface is put into a Partial power state. When a power down counter value is equal to a second value, a request for a Slumber power state is asserted, and Serial ATA interface is put into a Slumber power state.

Abstract: A device generally comprising a first circuit and a second circuit. The first circuit may be configured to (i) communicate with a host via a first bus (ii) using a small computer system interface (SCSI) protocol having a plurality of command descriptor blocks. The second circuit configured to (i) communicate with a remote device with a via a second bus, (ii) using an advanced technology attachment (ATA) protocol and (iii) translate a subset of the command descriptor blocks to the ATA protocol in application specific hardware.

Abstract: A foldable ironing board installation comprises an ironing board member, hinged to a lower panel member and connected thereto by a gas spring strut. The ironing board member can occupy a generally horizontal working position and an upright stowed position where it is coplanar with the lower panel member. An iron retention housing is arranged behind the lower panel member and stowed position of the ironing board member, and includes a surface which is inclined away from the member and to provide a rest for an iron so that the latter will rest against a wall of the housing.

Abstract: When a specific pair of devices are selected or reselected for communications across a SCSI bus, a hardware state machine in each device restores the communication parameters that have been previously negotiated for this pair of devices. This prevents the devices from wasting bus time for the restoration.

Abstract: A method and apparatus for generating a delay in the timing of a bus or other logic circuit such that changes may be made to timing parameters without undue hardware design changes is disclosed. A counter is used to count a number of clock cycles to time the delay. The number of clock cycles is pre-loaded into the counter from a memory. This eliminates the need for costly hardware design changes when timing parameters change, since all that must be changed is the number of clock cycles to be counted, which can be modified by replacing or reprogramming the memory.

Abstract: A foldable ironing board installation comprises an ironing board member, hinged to a lower panel member and connected thereto by a gas spring strut. The ironing board member can occupy a generally horizontal working position and an upright stowed position where it is coplanar with the lower panel member. An iron retention housing is arranged behind the lower panel member and stowed position of the ironing board member, and includes a surface which is inclined away from the member and to provide a rest for an iron so that the latter will rest against a wall of the housing.

Abstract: A method for defining electrical components enables a layout tool to include functionally extraneous cells in an integrated circuit design without significant adverse impact to the operation of the logically functional cells. The method defines the description of a first functionally extraneous cell for a layout tool so an initial layout of the die produced by the layout tool does not functionally couple the first functionally extraneous cell to a second functionally extraneous cell. The description of the functionally extraneous cell is altered so that the layout tool produces a second layout of the die that functionally couples the first and second functionally extraneous cells without altering the position of the second functionally extraneous cell with respect to a logically functional cell. The description of the functionally extraneous cell complies with the description constraints for cells.

Abstract: A system is disclosed that facilitates creation of a web-based user interface which obtains user profile information from a database, gathers information from one or more users regarding product characteristics, correlates the user responses, performs statistical analysis of the user responses and presents the statistical analysis in a user comprehendible manner. The system also stores statistical ratings in a database correlated to a particular product or service. Ratings are provided to a user from the database based on a particular product or service, and the database can be queried to retrieve one or more user profiles that have rated a product of interest to the current use.

Abstract: A method of interfacing a third circuit with a first circuit that operates based upon a first clock signal and a second circuit that operates based upon a second clock signal includes the step of applying the first clock signal and the second clock signal to a clock selector for the third circuit. The method further includes the step of transferring first data signals between the third circuit and the first circuit at a first rate based upon the first clock signal. Another step of the method includes causing the clock selector to apply the first clock signal to the third circuit prior to the step of transferring the first data signals between the third circuit and the first circuit. Yet another step of the method includes transferring second data signals between the third circuit and the second circuit at a second rate based upon the second clock signal.

Abstract: A system is disclosed that facilitates a web-based user interface to a particular application program that is enabled by obtaining user profile information, parsing the content of the particular application, matching the parsed content to user profile information and presenting the parsed content matches in a format based on information in the user's profile on a display. An innovative pattern matching system is integrated into the match processing to provide improved matching capability.

Abstract: A RAID controller integrated into a single chip. The RAID controller chip includes a general purpose RISC processor, memory interface logic, a host CPU PCI bus, at least one back-end I/O interface channel, at least one direct memory access (DMA) channel, and a RAID parity assist (RPA) circuit. The RAID chip enables higher integration of RAID functions within a printed circuit board and in particular enables RAID function integration directly on a personal computer or workstation motherboard. The back-end I/O interface channel is preferably dual SCSI channels. The RAID chip is operable in either of two modes. In a first mode, the chip provides pass through from the host CPU interface directly to the dual SCSI channels. This first mode of operation, a SCSI pass-through mode, allows use of the chip for non-RAID storage applications and enables low level manipulation of the disk array in RAID applications of the chip.

Abstract: Apparatus for evaluating the stability of the shoulder joint of a human subject includes a rotatable, elbow-holding assembly that has sensors and associated processing components for producing an indication of the rotational angle of the long axis of the humerus of the subject relative to a reference. Sensors measure muscle activity as the humerus is rotated. Changes in the muscle activity measurement are processed to produce an indication of the changes in the subject's apprehension as the humerus is moved. The apparatus may include a clock that indicates the times when muscle activity occurs. The levels of muscle activity may be recorded at different times and indicated to the operator. Pressure can be applied in a direction normal to the long axis of the humerus, and sensors produce an indication of the level of the applied pressure and corresponding apprehension of the subject. Also available is an indication of the level of muscle activity that occurs when such pressure is applied.