Abstract: A method and system to adjust a non-volatile cache associativity are described. In one embodiment, the method and system include determining a status of the system; and setting an associativity level of the non-volatile memory cache (NVC) of the system, based on that status of the system. In one embodiment, the non-volatile memory unit is a cache of the hard drive. Furthermore, in one embodiment, determining the status of the system includes determining whether the system is a mobile computer, and if so, determining whether the system is receiving power from a battery source or AC power from a wall outlet.

Abstract: Briefly, in accordance with an embodiment of the invention, a system and method to alter a cache policy of the system in response to the system transitioning from a first power state to a second power state is provided. The system may include a non-volatile disk cache and a disk memory, wherein the cache policy is used by the non-volatile disk cache to cache information for the disk memory.

Abstract: An apparatus and method for making changes to an active schedule being processed by a host controller is disclosed. The apparatus and method includes examining a transaction descriptor, determining a current state for a transaction based on the transaction descriptor, and preventing the transaction from starting if the current state indicates the transaction has not already started.

Abstract: A temperature sensitive memory, such as a ferroelectric polymer memory, may be utilized as a disk cache memory in one embodiment. If the temperature begins to threaten shutdown, the memory may be transitioned from a write-back to a write-through cache memory. In such case, the system is ready for shutdown without the loss of critical data.

Abstract: An apparatus, computing unit, and cable for attaching peripheral devices to a computer. A power hub contains both a bus hub and a power supply. The bus hub is capable of attaching peripheral devices to the computer. A cable connects the power hub to a computer. The cable carries both power from the power supply to the computer and data signals between the computer and the power hub.

Abstract: According to an embodiment of the invention, a method and apparatus for computer memory power backup are described. According to one embodiment, a memory system includes a first memory; a second memory coupled to the first memory and to a host, the second memory to transfer data between the first memory and the host; and a backup power source, the backup power source providing power to the first memory and the second memory if a main power source fails.

Abstract: A system, apparatus, and method are provided for memory backup and content preservation. According to one embodiment, a first memory bank of a memory, which is coupled to a computer bus, is reserved for a private use, and an isolation circuitry, which is coupled to the first memory bank, isolates the first memory bank from the computer bus in response to a signal indicating power failure received from and detected by a power failure/reduction detection unit, which is coupled to the isolation circuitry.

Abstract: A device is presented including a host controller capable of attaching a quantity of queue heads to a frame list. The quantity of queue heads are attached to the frame list before any transaction descriptors where split-isochronous transaction descriptors are supported.

Abstract: A device is presented including a host controller. A host controller driver is connected to the host controller. The host controller arranges queue element transfer descriptors (qTDs) in a circularly linked order. Also presented is a method including determining whether execution of a first queue element transfer descriptor (qTD) in a first bank including many qTDs results in a short packet condition. Following an alternate pointer in the first bank that points to a second bank if execution of the first qTD resulted in the short packet condition. Following a next pointer to a second qTD in the first bank if the execution of the first qTD completed normally. Also executing the second qTD in the first bank. The qTDs in the first bank and the second bank are circularly linked.

Abstract: A device is presented including a host controller. A host controller driver is connected to the host controller. The host controller arranges queue element transfer descriptors (qTDs) in a circularly linked order. Also presented is a method including determining whether execution of a first queue element transfer descriptor (qTD) in a first bank including many qTDs results in a short packet condition. Following an alternate pointer in the first bank that points to a second bank if execution of the first qTD resulted in the short packet condition. Following a next pointer to a second qTD in the first bank if the execution of the first qTD completed normally. Also executing the second qTD in the first bank. The qTDs in the first bank and the second bank are circularly linked.

Abstract: A device is presented including a host controller to generate a transaction schedule. The transaction schedule includes many transactions. The transactions are stored in many data structures. Each of the data structures contain initialized transactions or initialized and non-initialized transactions. The host controller executes the transactions that are initialized and the data structures each contain a pointer to the next initialized transaction.

Abstract: A device is presented including a host controller capable of attaching a quantity of queue heads to a frame list. The quantity of queue heads are attached to the frame list before any transaction descriptors. Further presented is a method including determining whether a queue head has less than or equal to a predetermined packet size and whether a period is one of greater than and equal to a predetermined schedule window. The method includes storing contents of a current entry in a frame list in a next pointer in the queue head. Also replacing the current entry in the frame list with a pointer to a new queue head. Many queue heads are directly coupled to the frame list.

Abstract: A device is presented including a host controller to generate a transaction schedule. The transaction schedule includes many transactions. The transactions are stored in many data structures. Each of the data structures contain initialized transactions or initialized and non-initialized transactions. The host controller executes the transactions that are initialized and the data structures each contain a pointer to the next initialized transaction.

Abstract: A timing enhancement for a USB controller determines if a short data packet is present. If so, data is placed in a buffer. If the buffer is full, data is sent. If the buffer is not full, the system looks to see if more data is available, if so takes it, if not it sends whatever is available.

Abstract: An apparatus and method for making changes to an active schedule being processed by a host controller is disclosed. The apparatus and method includes examining a transaction descriptor, determining a current state for a transaction based on the transaction descriptor, and preventing the transaction from starting if the current state indicates the transaction has not already started.

Abstract: A method and apparatus for generating, initializing, and scheduling of two interrupt queue heads to represent a single endpoint are described. In an embodiment, a method includes generating primary and secondary interrupt queue heads to represent a single interrupt endpoint. The method further includes initializing the primary and secondary interrupt queue heads. The method also includes scheduling the primary and secondary queue heads in immediately subsequent frames.

Abstract: A device is presented including a host controller capable of attaching a quantity of queue heads to a frame list. The quantity of queue heads are attached to the frame list before any transaction descriptors. Further presented is a method including determining whether a queue head has less than or equal to a predetermined packet size and whether a period is one of greater than and equal to a predetermined schedule window. The method includes storing contents of a current entry in a frame list in a next pointer in the queue head. Also replacing the current entry in the frame list with a pointer to a new queue head. Many queue heads are directly coupled to the frame list.

Abstract: A device is presented including a host controller. A host controller driver is connected to the host controller. The host controller arranges queue element transfer descriptors (qTDs) in a circularly linked order. Also presented is a method including determining whether execution of a first queue element transfer descriptor (qTD) in a first bank including many qTDs results in a short packet condition. Following an alternate pointer in the first bank that points to a second bank if execution of the first qTD resulted in the short packet condition. Following a next pointer to a second qTD in the first bank if the execution of the first qTD completed normally. Also executing the second qTD in the first bank. The qTDs in the first bank and the second bank are circularly linked.

Abstract: A user-initiated diagnostic test of a computer system is performed using a hardware abstraction layer including a diagnostic subsystem file and a diagnostic definition file, and also using diagnostic control routines and diagnostic status response routines. A selection is accepted from a user of a diagnostic subsystem to be tested from among a list of diagnostic subsystems stored in the diagnostic subsystem file. In accordance with information stored in the diagnostic definition file, the user is prompted for parameters of the selected diagnostic test, which are accepted from a user. These parameters are passed to the diagnostic control routine, which in response starts the selected diagnostic test. Diagnostic status response information from the diagnostic status response routine is received in the diagnostic control routine. The diagnostic status response information is presented to the user through a hardware-independent mechanism.