Patents by Inventor Brian A. Rinaldi
Brian A. Rinaldi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12105800Abstract: Provided are a computer program product, system, and method for using trap cache segments to detect malicious processes. A trap cache segment to the cache for data in the storage and indicated as a trap cache segment. Cache segments are added to the cache having data from the storage that are not indicated as trap cache segments. A memory function call from a process executing in the computer system reads data from a region of a memory device to output the read data to a buffer of the memory device. A determination is made as to whether the region of the memory device includes the trap cache segment. The memory function call is blocked and the process is treated as a potentially malicious process in response to determining that the region includes the trap cache segment.Type: GrantFiled: May 30, 2023Date of Patent: October 1, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian A. Rinaldi, Clint A. Hardy, Lokesh M. Gupta, Kevin J. Ash
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Patent number: 11785462Abstract: A device may include a memory and a processor. The device may receive, from a ground control station (GCS) associated with an unmanned aerial vehicle (UAV), credentials associated with a user. The device may determine whether the GCS has been registered and determine, in response to determining that the GCS has been registered, whether the UAV has been registered. The device may present, in response to determining that the UAV has been registered, a list of UAVs the user is authorized to operate and receive selection of a particular UAV from the list of UAVs. The device may facilitate operational activities of the particular UAV.Type: GrantFiled: December 31, 2020Date of Patent: October 10, 2023Assignee: Verizon Patent and Licensing Inc.Inventors: Dana Maher, Daniel William McMillan, David Brian Rinaldi, Jr., Jared Nelson Muirhead, Tera Lynn Schroeder
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Publication number: 20230306111Abstract: Provided are a computer program product, system, and method for using trap cache segments to detect malicious processes. A trap cache segment to the cache for data in the storage and indicated as a trap cache segment. Cache segments are added to the cache having data from the storage that are not indicated as trap cache segments. A memory function call from a process executing in the computer system reads data from a region of a memory device to output the read data to a buffer of the memory device. A determination is made as to whether the region of the memory device includes the trap cache segment. The memory function call is blocked and the process is treated as a potentially malicious process in response to determining that the region includes the trap cache segment.Type: ApplicationFiled: May 30, 2023Publication date: September 28, 2023Inventors: Brian A. Rinaldi, Clint A. Hardy, Lokesh M. Gupta, Kevin J. Ash
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Patent number: 11681799Abstract: Provided are a computer program product, system, and method for using trap cache segments to detect malicious processes. A trap cache segment to the cache for data in the storage and indicated as a trap cache segment. Cache segments are added to the cache having data from the storage that are not indicated as trap cache segments. A memory function call from a process executing in the computer system reads data from a region of a memory device to output the read data to a buffer of the memory device. A determination is made as to whether the region of the memory device includes the trap cache segment. The memory function call is blocked and the process is treated as a potentially malicious process in response to determining that the region includes the trap cache segment.Type: GrantFiled: December 23, 2020Date of Patent: June 20, 2023Assignee: INTERNATIONAL BUSINES MACHINES CORPORATIONInventors: Brian A. Rinaldi, Clint A. Hardy, Lokesh M. Gupta, Kevin J. Ash
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Patent number: 11550676Abstract: A method for protecting data in a storage system is disclosed. In one embodiment, such a method includes detecting, by a first hardware management console, first battery-on status associated with a first uninterruptible power supply. The method further detects, by a second hardware management console, second battery-on status associated with a second uninterruptible power supply. The method communicates, from the first hardware management console to the second hardware management console, the first battery-on status. The method then triggers, by the second hardware management console, a dump of modified data from memory to more persistent storage upon detecting both the first battery-on status and the second battery-on status. A corresponding system and computer program product are also disclosed.Type: GrantFiled: September 6, 2018Date of Patent: January 10, 2023Assignee: International Business Machines CorporationInventors: Todd C. Sorenson, Ronald D. Martens, Keith G. Morrison, Brian A. Rinaldi, Jiwu Duan, John C. Elliott, Gary W. Batchelor
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Patent number: 11442826Abstract: A method for reducing incidents of data loss in redundant arrays of independent disks (RAIDs) having the same RAID level is disclosed. In one embodiment, such a method identifies, in a data storage environment, a set of RAIDs having a common RAID level. The method also identifies, in the set of RAIDs, higher risk storage drives having a failure risk above a threshold and lower risk storage drives having a failure risk below the threshold. The method swaps, within the RAIDs, higher risk storage drives with lower risk storage drives to more evenly distribute higher risk storage drives across the RAIDs. A corresponding system and computer program product are also disclosed.Type: GrantFiled: June 15, 2019Date of Patent: September 13, 2022Assignee: International Business Machines CorporationInventors: Lokesh M. Gupta, Matthew G. Borlick, Karl A. Nielsen, Clint A. Hardy, Brian A. Rinaldi
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Patent number: 11416147Abstract: A method for protecting data in a storage system is disclosed. In one embodiment, such a method includes detecting, by a first rack power controller, first battery-on status associated with a first uninterruptible power supply. The method further detects, by a second rack power controller, second battery-on status associated with a second uninterruptible power supply. The method communicates, from the first rack power controller to the second rack power controller, the first battery-on status. The method then triggers, by the second rack power controller, a dump of modified data from memory to more persistent storage upon detecting both the first battery-on status and the second battery-on status. A corresponding system and computer program product are also disclosed.Type: GrantFiled: September 6, 2018Date of Patent: August 16, 2022Assignee: International Business Machines CorporationInventors: Todd C. Sorenson, Brian A. Rinaldi, John C. Elliott, Gary W. Batchelor, Jiwu Duan
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Publication number: 20220210644Abstract: A device may include a memory and a processor. The device may receive, from a ground control station (GCS) associated with an unmanned aerial vehicle (UAV), credentials associated with a user. The device may determine whether the GCS has been registered and determine, in response to determining that the GCS has been registered, whether the UAV has been registered. The device may present, in response to determining that the UAV has been registered, a list of UAVs the user is authorized to operate and receive selection of a particular UAV from the list of UAVs. The device may facilitate operational activities of the particular UAV.Type: ApplicationFiled: December 31, 2020Publication date: June 30, 2022Inventors: Dana Maher, Daniel William McMillan, David Brian Rinaldi, JR., Jared Nelson Muirhead, Tera Lynn Schroeder
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Patent number: 11226899Abstract: Provided are a computer program product, system, and method for populating a second cache with tracks from a first cache when transferring management of the tracks from a first node to a second node. Management of a first group of tracks in the storage managed by the first node is transferred to the second node managing access to a second group of tracks in the storage. After the transferring the management of the tracks, the second node manages access to the first and second groups of tracks and caches accessed tracks from the first and second groups in the second cache of the second node. The second cache of the second node is populated with the tracks in a first cache of the first node.Type: GrantFiled: July 24, 2019Date of Patent: January 18, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta, Matthew J. Kalos, Brian A. Rinaldi
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Patent number: 11080397Abstract: Provided are a computer program product, system, and method for using trap cache segments to detect malicious processes. A trap cache segment to the cache for data in the storage and indicated as a trap cache segment. Cache segments are added to the cache having data from the storage that are not indicated as trap cache segments. A memory function call from a process executing in the computer system reads data from a region of a memory device to output the read data to a buffer of the memory device. A determination is made as to whether the region of the memory device includes the trap cache segment. The memory function call is blocked and the process is treated as a potentially malicious process in response to determining that the region includes the trap cache segment.Type: GrantFiled: September 12, 2018Date of Patent: August 3, 2021Assignee: International Business Machines CorporationInventors: Brian A. Rinaldi, Clint A. Hardy, Lokesh M. Gupta, Kevin J. Ash
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Patent number: 11074118Abstract: A method for reporting incidents of data loss in a storage environment comprising redundant arrays of independent disks (RAIDs) is disclosed. In one embodiment, such a method monitors storage drive failures in a storage environment. For a storage drive failure detected in the storage environment, the method reports the RAID type in which the storage drive failure occurred and whether data loss occurred in the RAID as a result of the storage drive failure. In certain embodiments, the method reports whether the data loss could have been prevented had the RAID type been converted to a more robust RAID type. In other or the same embodiments, the method reports whether the data loss was prevented by the RAID type. A corresponding system and computer program product are also disclosed.Type: GrantFiled: June 15, 2019Date of Patent: July 27, 2021Assignee: International Business Machines CorporationInventors: Lokesh M. Gupta, Matthew G. Borlick, Karl A. Nielsen, Clint A. Hardy, Brian A. Rinaldi
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Patent number: 11042636Abstract: Provided are a computer program product, system, and method for detecting potentially malicious code in a host system accessing data from a storage. A trap storage unit is configured for data in the storage and the trap storage unit is indicated as a trap. Storage units are configured for data in the storage that are not indicated as a trap. A request is received to access the trap storage unit from a process executing in a host system. Notification is returned to the host system that the process requesting to access the trap storage unit is a potentially malicious process.Type: GrantFiled: September 12, 2018Date of Patent: June 22, 2021Assignee: International Business Machines CorporationInventors: Brian A. Rinaldi, Clint A. Hardy, Lokesh M. Gupta, Kevin J. Ash
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Patent number: 11016851Abstract: A machine learning module receives inputs comprising attributes of a storage controller, where the attributes affect failures that occur in the storage controller. In response to a failure occurring in the storage controller, a plurality of output values corresponding to a plurality of recovery mechanisms to recover from the failure in the storage controller are generated via forward propagation through a plurality of layers of the machine learning module. A margin of error is calculated based on comparing the generated output values to expected output values corresponding to the plurality of recovery mechanisms, where the expected output values are generated from an indication of a correct recovery mechanism for the failure. An adjustment is made of weights of links that interconnect nodes of the plurality of layers via back propagation to reduce the margin of error, to improve a determination of a recovery mechanism for the failure.Type: GrantFiled: November 8, 2018Date of Patent: May 25, 2021Assignee: International Business Machines CorporationInventors: Brian A. Rinaldi, Clint A. Hardy, Lokesh M. Gupta
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Patent number: 11016692Abstract: A method to dynamically switch between data transfer techniques includes receiving an I/O request and computing a cost of executing the I/O request using a memory copy data transfer technique. The memory copy data transfer technique copies cache segments associated with the I/O request from cache memory to a permanently mapped memory, which is permanently mapped to a bus address window. The method also computes a cost of executing the I/O request using a memory mapping data transfer technique. The memory mapping data transfer technique temporarily maps cache segments associated with the I/O request from the cache memory to the bus address window. The method uses one of the memory copy data transfer technique and the memory mapping data transfer technique to transfer cache segments associated with the I/O request, depending on which one is less costly. A corresponding system and computer program product are also disclosed.Type: GrantFiled: September 11, 2019Date of Patent: May 25, 2021Assignee: International Business Machines CorporationInventors: Lokesh M. Gupta, Kevin J. Ash, Brian A. Rinaldi, Kyler A. Anderson, Matthew J. Kalos
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Publication number: 20210117541Abstract: Provided are a computer program product, system, and method for using trap cache segments to detect malicious processes. A trap cache segment to the cache for data in the storage and indicated as a trap cache segment. Cache segments are added to the cache having data from the storage that are not indicated as trap cache segments. A memory function call from a process executing in the computer system reads data from a region of a memory device to output the read data to a buffer of the memory device. A determination is made as to whether the region of the memory device includes the trap cache segment. The memory function call is blocked and the process is treated as a potentially malicious process in response to determining that the region includes the trap cache segment.Type: ApplicationFiled: December 23, 2020Publication date: April 22, 2021Inventors: Brian A. Rinaldi, Clint A. Hardy, Lokesh M. Gupta, Kevin J. Ash
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Patent number: 10976941Abstract: A peer to peer remote copy operation is performed between a primary storage controller and a secondary storage controller, to establish a peer to peer remote copy relationship between a primary storage volume and a secondary storage volume. Subsequent to indicating completion of the peer to peer remote copy operation to a host, a determination is made as to whether the primary storage volume and the secondary storage volume have identical data, by performing operations of staging data of the primary storage volume from auxiliary storage of the primary storage controller to local storage of the primary storage controller, and transmitting the data of the primary storage volume that is staged, to the secondary storage controller for comparison with data of the secondary storage volume stored in an auxiliary storage of the secondary storage controller.Type: GrantFiled: January 15, 2020Date of Patent: April 13, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew G. Borlick, Lokesh M. Gupta, Brian A. Rinaldi, Micah Robison
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Patent number: 10956148Abstract: Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure management engine on each of a plurality of server nodes that code activation for a first set of I/O enclosures is starting. An update image is distributed to the first set of I/O enclosures. The update image on the first set of I/O enclosures is activated by sending an activate reset command to each of the first set of I/O enclosures, wherein a reset is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures in response to determining that the reset is an activate reset. In response to the activate reset command completing, second notifications are sent to each I/O enclosure management engine that code activation for the first set of I/O enclosures has completed.Type: GrantFiled: November 14, 2019Date of Patent: March 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gary W. Batchelor, Veronica S. Davila, Enrique Q. Garcia, Robin Han, Jay T. Kirch, Ronald D. Martens, Trung N. Nguyen, Brian A. Rinaldi, Todd C. Sorenson
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DYNAMICALLY ADJUSTING A NUMBER OF MEMORY COPY AND MEMORY MAPPING WINDOWS TO OPTIMIZE I/O PERFORMANCE
Publication number: 20210073136Abstract: A method to dynamically optimize utilization of data transfer techniques includes processing multiple I/O requests using one of several data transfer techniques depending on which data transfer technique is more efficient. The data transfer techniques include: a memory copy data transfer technique that copies cache segments associated with an I/O request from a cache memory to a permanently mapped memory; and a memory mapping data transfer technique that temporarily maps cache segments associated with an I/O request. In order to process the I/O requests, the method utilizes a first number of “copy” windows associated with the memory copy data transfer technique, and a second number of “mapping” windows associated with the memory mapping data transfer technique. The method dynamically adjusts one or more of the first number and the second number to optimize the processing of the I/O requests. A corresponding system and computer program product are also disclosed.Type: ApplicationFiled: September 11, 2019Publication date: March 11, 2021Applicant: International Business Machines CorporationInventors: Lokesh M. Gupta, Kevin J. Ash, Kyler A. Anderson, Brian A. Rinaldi -
Publication number: 20210072918Abstract: A method to dynamically switch between data transfer techniques includes receiving an I/O request and computing a cost of executing the I/O request using a memory copy data transfer technique. The memory copy data transfer technique copies cache segments associated with the I/O request from cache memory to a permanently mapped memory, which is permanently mapped to a bus address window. The method also computes a cost of executing the I/O request using a memory mapping data transfer technique. The memory mapping data transfer technique temporarily maps cache segments associated with the I/O request from the cache memory to the bus address window. The method uses one of the memory copy data transfer technique and the memory mapping data transfer technique to transfer cache segments associated with the I/O request, depending on which one is less costly. A corresponding system and computer program product are also disclosed.Type: ApplicationFiled: September 11, 2019Publication date: March 11, 2021Applicant: International Business Machines CorporationInventors: Lokesh M. Gupta, Kevin J. Ash, Brian A. Rinaldi, Kyler A. Anderson, Matthew J. Kalos
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Dynamically adjusting a number of memory copy and memory mapping windows to optimize I/O performance
Patent number: 10942857Abstract: A method to dynamically optimize utilization of data transfer techniques includes processing multiple I/O requests using one of several data transfer techniques depending on which data transfer technique is more efficient. The data transfer techniques include: a memory copy data transfer technique that copies cache segments associated with an I/O request from a cache memory to a permanently mapped memory; and a memory mapping data transfer technique that temporarily maps cache segments associated with an I/O request. In order to process the I/O requests, the method utilizes a first number of “copy” windows associated with the memory copy data transfer technique, and a second number of “mapping” windows associated with the memory mapping data transfer technique. The method dynamically adjusts one or more of the first number and the second number to optimize the processing of the I/O requests. A corresponding system and computer program product are also disclosed.Type: GrantFiled: September 11, 2019Date of Patent: March 9, 2021Assignee: International Business Machines CorporationInventors: Lokesh M. Gupta, Kevin J. Ash, Kyler A. Anderson, Brian A. Rinaldi