Abstract: An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.

Abstract: A method includes over-programming thin film storage (TFS) memory cells on a semiconductor wafer with a first voltage that is higher than a highest voltage used to program the memory cells during normal operation of the memory cells. With the memory cells in an over-programmed state, the wafer is exposed to a first temperature above a product specification temperature for a period of time sufficient to induce redistribution of charge among storage elements in the memory cells.

Abstract: A semiconductor device includes a semiconductor substrate, a charge storage stack over a portion of the substrate. The charge storage stack includes a first dielectric layer, a layer of nanocrystals in contact with the first dielectric layer, a second dielectric layer over and in contact with the layer of nanocrystals, a nitride layer over and in contact with the second dielectric layer, and a third dielectric layer over the nitride layer.

Abstract: Making a non-volatile memory (NVM) structure uses a semiconductor substrate. One embodiment includes forming a select gate structure including a first dummy material on the semiconductor substrate and forming a control gate structure including a second dummy material on the semiconductor substrate, where the first dummy material is different from the second dummy material. The embodiment also includes replacing the first dummy material with metal and replacing the second dummy material with polysilicon.

Abstract: A method of making a split gate non-volatile memory (NVM) includes forming a charge storage layer on the substrate, depositing a first conductive layer, and depositing a capping layer. These layers are patterned to form a control gate stack. A second conductive layer is deposited over the substrate and is patterned to leave a first portion of the second conductive layer over a portion of the control gate stack and adjacent to a first side of the control gate stack. The first portion of the second conductive layer and the control gate stack are planarized to leave a dummy select gate from the first portion of the second conductive layer, where a top surface of a remaining portion of the first conductive layer is lower relative to a top surface of the dummy select gate. The dummy select gate is replaced with a select gate including metal.

Abstract: Split-gate non-volatile memory (NVM) cells having gap protection zones are disclosed along with related manufacturing methods. After formation of a gate for a split-gate NVM cell over a substrate, a doped region is formed adjacent the gate. A first portion of the doped region is then removed to leave a second portion of the doped region that forms a gap protection zone adjacent the gate. For some disclosed embodiments, a select gate is formed before a control gate. For other disclosed embodiments, the control gate is formed before the select gate. The gap protection zones can be formed, for example, using an etch processing step to remove the desired portions of the doped region, and a spacer can also be used to protect the gap protection zone during this etch processing step. Related NVM systems are also disclosed.

Abstract: Semiconductor structures and methods for making semiconductor structures include a split gate non-volatile memory (NVM) cell in an NVM region. A charge storage layer, a first conductive layer, and a capping layer are formed over the substrate, which are patterned to form a control gate stack in the NVM region of the substrate. A high-k dielectric layer, a metal layer, and a second conductive layer are formed over the substrate. The second conductive layer and the metal layer are patterned to form remaining portions of the second conductive layer and the metal layer over and adjacent to a first side of the control gate stack. The remaining portion of the second conductive layer is removed to form a select gate stack, which includes the remaining portion of the metal layer. A stressor layer is formed over the substrate.

Abstract: Semiconductor structures and methods for making semiconductor structures include a split gate non-volatile memory (NVM) cell in an NVM region. A charge storage layer, a first conductive layer, and a capping layer are formed over the substrate, which are patterned to form a control gate stack in the NVM region of the substrate. A high-k dielectric layer, a metal layer, and a second conductive layer are formed over the substrate. The second conductive layer and the metal layer are patterned to form remaining portions of the second conductive layer and the metal layer over and adjacent to a first side of the control gate stack. The remaining portion of the second conductive layer is removed to form a select gate stack, which includes the remaining portion of the metal layer. A stressor layer is formed over the substrate.

Abstract: A method of making a split gate non-volatile memory (NVM) includes forming a charge storage layer on the substrate, depositing a first conductive layer, and depositing a capping layer. These layers are patterned to form a control gate stack. A second conductive layer is deposited over the substrate and is patterned to leave a first portion of the second conductive layer over a portion of the control gate stack and adjacent to a first side of the control gate stack. The first portion of the second conductive layer and the control gate stack are planarized to leave a dummy select gate from the first portion of the second conductive layer, where a top surface of a remaining portion of the first conductive layer is lower relative to a top surface of the dummy select gate. The dummy select gate is replaced with a select gate including metal.

Abstract: A semiconductor device includes a semiconductor substrate, a charge storage stack over a portion of the substrate. The charge storage stack includes a first dielectric layer, a layer of nanocrystals in contact with the first dielectric layer, a second dielectric layer over and in contact with the layer of nanocrystals, a nitride layer over and in contact with the second dielectric layer, and a third dielectric layer over the nitride layer.

Abstract: Making a non-volatile memory (NVM) structure uses a semiconductor substrate. One embodiment includes forming a select gate structure including a first dummy material on the semiconductor substrate and forming a control gate structure including a second dummy material on the semiconductor substrate, where the first dummy material is different from the second dummy material. The embodiment also includes replacing the first dummy material with metal and replacing the second dummy material with polysilicon.

Abstract: A method of making a non-volatile memory cell includes forming a plurality of discrete storage elements. A tensile dielectric layer is formed among the discrete storage elements and provides lateral tensile stress to the discrete storage elements. A gate is formed over the discrete storage elements.

Abstract: A process integration is disclosed for fabricating non-volatile memory (NVM) cells having spacer control gates (108) along with a high-k-metal-poly select gate (121, 123, 127) and one or more additional in-laid high-k metal CMOS transistor gates (121, 124, 128) using a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.

Abstract: Embodiments include a split-gate non-volatile memory cell that is formed having a control gate and a select gate, where at least a portion of the control gate is formed over the select gate. A charge storage layer is formed between the select gate and the control gate. The select gate is formed using a first conductive layer and a second conductive layer. The second conductive layer is formed over the first conductive layer and has a lower resistivity than the first conductive layer. In one embodiment, the first conductive layer is polysilicon and the second conductive layer is titanium nitride (TiN). In another embodiment, the second conductive layer may be a silicide or other conductive material, or combination of conductive materials having a lower resistivity than the first conductive layer.

Abstract: A process integration is disclosed for fabricating non-volatile memory (NVM) cells having spacer control gates (108) along with a high-k-metal-poly select gate (121, 123, 127) and one or more additional in-laid high-k metal CMOS transistor gates (121, 124, 128) using a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.

Abstract: Split-gate non-volatile memory (NVM) cells having gap protection zones are disclosed along with related manufacturing methods. After formation of a gate for a split-gate NVM cell over a substrate, a doped region is formed adjacent the gate. A first portion of the doped region is then removed to leave a second portion of the doped region that forms a gap protection zone adjacent the select gate. For some disclosed embodiments, a select gate is formed before a control gate for the split-gate NVM cell. For other disclosed embodiments, the control gate is formed before the select gate for the split-gate NVM cell. The gap protection zones can be formed, for example, using an etch processing step to remove the desired portions of the doped region, and a spacer can also be used to protect the gap protection zone during this etch processing step. Related NVM systems are also disclosed.

Abstract: A method of making a semiconductor structure uses a substrate having a background doping of a first type. A gate structure has a gate dielectric on the substrate and a select gate layer on the gate dielectric. Implanting is performed into a first portion of the substrate adjacent to a first end with dopants of a second type. The implanting is prior to any dopants being implanted into the background doping of the first portion which becomes a first doped region of the second type. An NVM gate structure has a select gate, a storage layer having a first portion over the first doped region, and a control gate over the storage layer. Implanting at a non-vertical angle with dopants of the first type forms a deep doped region under the select gate. Implanting with dopants of the second type forms a source/drain extension.

Abstract: A first transistor and a second transistor are formed with different threshold voltages. A first gate is formed over the first region of a substrate for a first transistor and a second gate over the second region for a second transistor. The first region is masked. A threshold voltage of the second transistor is adjusted by implanting through the second gate while masking the first region. Current electrode regions are formed on opposing sides of the first gate and current electrode regions on opposing sides of the second gate.

Abstract: A method of making a semiconductor structure uses a substrate having a background doping of a first type. A gate structure has a gate dielectric on the substrate and a select gate layer on the gate dielectric. Implanting is performed into a first portion of the substrate adjacent to a first end with dopants of a second type. The implanting is prior to any dopants being implanted into the background doping of the first portion which becomes a first doped region of the second type. An NVM gate structure has a select gate, a storage layer having a first portion over the first doped region, and a control gate over the storage layer. Implanting at a non-vertical angle with dopants of the first type forms a deep doped region under the select gate. Implanting with dopants of the second type forms a source/drain extension.

Abstract: A method of making a non-volatile memory (NVM) cell using a substrate having a top surface of silicon includes forming a select gate stack over the substrate. An oxide layer is grown on the top surface of the substrate. Nanocrystals of silicon are formed on the thermal oxide layer adjacent to a first side the select gate stack. The nanocrystals are partially oxidized to result in partially oxidized nanocrystals and further growing the thermal oxide layer. A control gate is formed over the partially oxidized nanocrystals. A first doped region is formed in the substrate adjacent to a first side of the control gate and a second doped region in the substrate adjacent to a second side of the select gate.