Abstract: Systems and methods for protecting external memory resources to prevent bandwidth collapse in a network processor. One embodiment is a network processor including an input port configured to receive packets from a source device, on-chip memory configured to store packets in queues, and external memory configured to provide a backing store to the on-chip memory. The network processor also includes a processor configured, in response to determining that the source device is unresponsive to a congestion notification, to reduce a size of one or more queues to prevent packets transferring from the on-chip memory to the external memory.

Abstract: Systems and methods for protecting external memory resources to prevent bandwidth collapse in a network processor. One embodiment is a network processor including an input port configured to receive packets from a source device, on-chip memory configured to store packets in queues, an external memory interface configured to couple the on-chip memory with an external memory providing a backing store to the on-chip memory, and bandwidth monitor configured to measure a bandwidth utilization of the external memory. The network processor also includes a processor configured to apply the bandwidth utilization of the external memory to a congestion notification profile, to generate one or more congestion notifications based on the bandwidth utilization applied to the congestion notification profile, and to send the one or more congestion notifications to the source device to request decreasing packet rate for decreasing the bandwidth utilization of the external memory.

Abstract: Systems and methods for flowlet switching using memory instructions. One embodiment is a method of distributing packets over multiple paths. The method includes determining an elapsed time between a packet and a previous packet. The method further includes, in response to determining that the elapsed time is less than an inter-packet gap threshold: retaining a previously selected path value indicated in the flow record, and providing the previously selected path value to the processing thread for transmitting the packet over a previously selected path associated with the previous packet. The method also further includes, in response to determining that the elapsed time is greater than the inter-packet gap threshold: updating the flow record by replacing the previously selected path value with the path value of the selected path of the memory instruction, and providing the path value to the processing thread for transmitting the packet over the selected path.

Abstract: Systems and methods for protecting external memory resources to prevent bandwidth collapse in a network processor. One embodiment is a network processor including an input port configured to receive packets from a source device, on-chip memory configured to store packets in queues, and external memory configured to provide a backing store to the on-chip memory. The network processor also includes a processor configured, in response to determining that the source device is unresponsive to a congestion notification, to reduce a size of one or more queues to prevent packets transferring from the on-chip memory to the external memory.

Abstract: Switch fabric in routers require tight characteristics in term of packet loss, fairness in bandwidth allocation and low latency for high-priority traffic. Such attributes have been resolved using specialized switch devices, but with the emergence of Data Center Bridging, the possibility of using commodity Ethernet switches to build switch fabric in routers is considered. Systems and methods are provided for estimating congestion associated with a network path in accordance with the variation in average delay experienced by samples of packets.

Abstract: A device for determining oversubscription of a first virtualized network function (70) in order to enable flow control in the virtualization of at least one node in a communication network comprises a first virtualized network function (70) having packet handling resources comprising at least one queue (108, 112, 114, 120) and being a downstream network function located downstream from at least one second upstream network function in a packet flow between the network functions. The device comprises flow control functionality (79) set to monitor at least one queue (108, 112, 114, 120), determine if the first virtualized network function (70) is oversubscribed based on the monitoring, and generate, in case the first virtualized network function is determined to be oversubscribed, an instruction for at least one upstream network function to change its transmission rate to the first virtualized network function (70) in order to reduce the oversubscription.

Abstract: A device for determining oversubscription of a first virtualized network function (70) in order to enable flow control in the virtualization of at least one node in a communication network comprises a first virtualized network function (70) having packet handling resources comprising at least one queue (108, 112, 114, 120) and being a downstream network function located downstream from at least one second upstream network function in a packet flow between the network functions. The device comprises flow control functionality (79) set to monitor at least one queue (108, 112, 114, 120), determine if the first virtualized network function (70) is oversubscribed based on the monitoring, and generate, in case the first virtualized network function is determined to be oversubscribed, an instruction for at least one upstream network function to change its transmission rate to the first virtualized network function (70) in order to reduce the oversubscription.

Abstract: Switch fabric in routers require tight characteristics in term of packet loss, fairness in bandwidth allocation and low latency for high-priority traffic. Such attributes have been resolved using specialized switch devices, but with the emergence of Data Center Bridging, the possibility of using commodity Ethernet switches to build switch fabric in routers is considered. Systems and methods are provided for estimating congestion associated with a network path in accordance with the variation in average delay experienced by samples of packets.

Abstract: Switch fabric in routers require tight characteristics in term of packet loss, fairness in bandwidth allocation and low latency for high-priority traffic. Such attributes have been resolved using specialized switch devices, but with the emergence of Data Center Bridging, the possibility of using commodity Ethernet switches to build switch fabric in routers is considered. Systems and methods are provided for adjusting a data transmission rate in accordance with an estimation of network path utilization.

Abstract: Switch fabric in routers require tight characteristics in term of packet loss, fairness in bandwidth allocation and low latency for high-priority traffic. Such attributes have been resolved using specialized switch devices, but with the emergence of Data Center Bridging, the possibility of using commodity Ethernet switches to build switch fabric in routers is considered. Systems and methods are provided for adjusting a data transmission rate in accordance with an estimation of network path utilization.

Abstract: A method of operating a load balancing switch may include providing a flow entry in a flow table, the flow entry may include a match pattern that is satisfied by a data flow identification, and the flow entry may identify a first server. A first data packet including a first data flow identification may be received, and the first data packet may be transmitted to the first server responsive to the first data flow identification satisfying the match pattern. After transmitting the first data packet to the first server, the flow entry may be modified so that the flow entry identifies the first server and a second server. After modifying the flow entry, a second data packet including a second data flow identification may be received, and the second data packet may be transmitted to the first and second servers responsive to the second data flow identification satisfying the match pattern.

Abstract: A method of operating a load balancing switch may include providing a flow entry in a flow table, the flow entry may include a match pattern that is satisfied by a data flow identification, and the flow entry may identify a first server. A first data packet including a first data flow identification may be received, and the first data packet may be transmitted to the first server responsive to the first data flow identification satisfying the match pattern. After transmitting the first data packet to the first server, the flow entry may be modified so that the flow entry identifies the first server and a second server. After modifying the flow entry, a second data packet including a second data flow identification may be received, and the second data packet may be transmitted to the first and second servers responsive to the second data flow identification satisfying the match pattern.

Abstract: A method executed by a controller of a plurality of processing elements to reduce processing time of a data packet in a network element. The processing elements are arranged in a matrix. Each processing element has a point to point connection with each adjacent processing element, known as a hop. Each processing element also includes a separate processing element storage. The data packet includes a data and a descriptor, the data being transmitted to a first processing element for storage before the descriptor is received by the controller, and the data being processed after the descriptor is received. The method includes receiving the descriptor at the controller, determining that the first processing element does not have an available resource for processing the data, determining a second processing element based on a least number of hops to the first processing element, and transmitting the descriptor to the second processing element.

Abstract: A method in a network device. The method is one of estimating a time delay between when a software timestamp is generated for an active measurement protocol test packet and when the active measurement protocol test packet is transmitted from the network device onto a link. The method includes generating an error estimation packet, generating a software timestamp (ts) for the error estimation packet, and transmitting the error estimation packet toward a network interface. The method also includes intercepting the error estimation packet before it is transmitted from the network device onto the link, and generating an interception timestamp (ti) for the error estimation packet after intercepting the error estimation packet. The time delay is estimated based on a difference between the interception timestamp and the software timestamp.

Abstract: Embodiments of the invention include a method for avoiding memory bandwidth utilization during packet processing. The packet processing core receives a plurality of packets. The packet processing core identifies the packet's quality of service (QoS) descriptor. The packet processing core determines that at least one packet should be moved to an off-chip packet stored prior to the packet being transmitted to the egress port. The packet processing core bases that determination, at least in part, on the packet's QoS descriptor. The packet processing core moves the determined packets to the off-chip packet store. The packet processing core determines that at least one packet should not be moved to the off-chip packet store prior to the packet being transmitted to the egress port. This determination is also made, at least in part, based on the packet's QoS descriptor.

Abstract: Embodiments of the invention a method for policing a packet at line rate. A hierarchical policer receives a policer request comprising packet characteristics and identifying request configuration information. The hierarchical policer retrieves meter states specified by the request configuration information. The hierarchical policer processes packet characteristics through meters to generate a meter result. The hierarchical policer generates a hierarchical policer table lookup address using a plurality of meter types, a plurality of input color controls, one or more of the packet characteristics, the meter results, and a plurality of coupling algorithm identifiers. The hierarchical policer reads a hierarchical meter result from a hierarchical policer result table, containing at least a final output packet attribute that classifies the packet. The hierarchical policer updates one or more of the meter states based on the plurality of meter state results.

Abstract: A method performed in a memory controller for maintaining segmented counters split into primary and secondary memories, the primary memory faster. Events occur that require incrementing one of the segmented counters and the memory controller responds by incrementing a corresponding primary part in the primary memory. Each time a primary part is rolling over the memory controller determines that a secondary part should be updated. Also, the memory controller periodically determines that the secondary part of a segmented counter should be opportunistically updated. The opportunistic update is based on a probability function and a random number. The secondary part includes at least all of bits of the segmented counter not in the primary part and is stored in the secondary memory. Each time an update to the secondary part occurs, both the secondary part and primary part of the segmented counter must be updated.

Abstract: Embodiments of the invention include a method performed in a packet processor core for policing a packet through a hierarchical policer coupled to one or more policing requestors. The hierarchical policer has a plurality of meter levels including an initial level and one or more subsequent levels. The hierarchical policer creates a meter result at the meter of each meter level using packet characteristics and a meter state for that meter level. The hierarchical policer generates meter level outputs that classify the packet for each meter level and for at least one of the subsequent levels the meter level output is based on the meter level output from a previous meter level. The hierarchical policer performs a meter combine operation that produces a final packet output attribute from the combination of the meter level outputs. The hierarchical policer returns the final packet output attribute to a policing requestor.

Abstract: Embodiments of the invention include a method performed by a bank aware mtrie control module for distributing a plurality of mtrie levels across a plurality of memory banks. The bank aware mtrie control module identifies the plurality of memory banks present and identifies one or more mtrie blocks in one or more mtrie levels, each mtrie block is an array of mtrie nodes associated with an mtrie level. The bank aware mtrie control module stores each mtrie block in one of the plurality of memory banks, all mtrie nodes in a given mtrie block are stored in the same memory bank. For each subsequent mtrie level, the bank aware mtrie control module ensures that each of the mtrie blocks in that mtrie level is stored in one of the plurality of memory banks other than the memory bank storing mtrie blocks of an immediately previous mtrie level.

Abstract: A network element that includes multiple memory types and memory sizes translates a logical memory address into a physical memory address. A memory access request is received for a data structure with a logical memory address that includes a region identifier that identifies a region that is mapped to one or more memories and is associated with a set of one or more region attributes whose values are based on processing requirements provided by a software programmer and the available memories of the network element. The network element accesses the region mapping table entry corresponding to the region identifier and, using the region attributes that are associated with the region, determines an access target for the request, determines a physical memory address offset within the access target, and generates a physical memory address. The access target includes a target class of memory, an instance within the class of memory, and a particular physical address space of the instance within the class of memory.